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wdenkaffae2b2002-08-17 09:36:01 +00001/*-----------------------------------------------------------------------------+
Josh Boyer471573b2009-08-07 13:53:20 -04002 | This source code is dual-licensed. You may use it under the terms of the
3 | GNU General Public License version 2, or under the license below.
wdenkaffae2b2002-08-17 09:36:01 +00004 |
Stefan Roese0c7ffc02005-08-16 18:18:00 +02005 | This source code has been made available to you by IBM on an AS-IS
6 | basis. Anyone receiving this source is licensed under IBM
7 | copyrights to use it in any way he or she deems fit, including
8 | copying it, modifying it, compiling it, and redistributing it either
9 | with or without modifications. No license under IBM patents or
10 | patent applications is to be implied by the copyright license.
wdenkaffae2b2002-08-17 09:36:01 +000011 |
Stefan Roese0c7ffc02005-08-16 18:18:00 +020012 | Any user of this software should understand that IBM cannot provide
13 | technical support for this software and will not be responsible for
14 | any consequences resulting from the use of this software.
wdenkaffae2b2002-08-17 09:36:01 +000015 |
Stefan Roese0c7ffc02005-08-16 18:18:00 +020016 | Any person who transfers this source code or any derivative work
17 | must include the IBM copyright notice, this paragraph, and the
18 | preceding two paragraphs in the transferred software.
wdenkaffae2b2002-08-17 09:36:01 +000019 |
Stefan Roese0c7ffc02005-08-16 18:18:00 +020020 | COPYRIGHT I B M CORPORATION 1995
21 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
wdenkaffae2b2002-08-17 09:36:01 +000022 +-----------------------------------------------------------------------------*/
23/*-----------------------------------------------------------------------------+
24 |
Stefan Roese0c7ffc02005-08-16 18:18:00 +020025 | File Name: miiphy.c
wdenkaffae2b2002-08-17 09:36:01 +000026 |
Stefan Roese0c7ffc02005-08-16 18:18:00 +020027 | Function: This module has utilities for accessing the MII PHY through
wdenkaffae2b2002-08-17 09:36:01 +000028 | the EMAC3 macro.
29 |
Stefan Roese0c7ffc02005-08-16 18:18:00 +020030 | Author: Mark Wisner
wdenkaffae2b2002-08-17 09:36:01 +000031 |
wdenkaffae2b2002-08-17 09:36:01 +000032 +-----------------------------------------------------------------------------*/
33
Stefan Roese8b231b22008-02-19 21:58:25 +010034/* define DEBUG for debugging output (obviously ;-)) */
35#if 0
36#define DEBUG
37#endif
38
wdenkaffae2b2002-08-17 09:36:01 +000039#include <common.h>
40#include <asm/processor.h>
Stefan Roese697100952007-10-23 14:03:17 +020041#include <asm/io.h>
wdenkaffae2b2002-08-17 09:36:01 +000042#include <ppc_asm.tmpl>
43#include <commproc.h>
Stefan Roese247e9d72010-09-09 19:18:00 +020044#include <asm/ppc4xx-emac.h>
45#include <asm/ppc4xx-mal.h>
wdenkaffae2b2002-08-17 09:36:01 +000046#include <miiphy.h>
47
Stefan Roese8b231b22008-02-19 21:58:25 +010048#if !defined(CONFIG_PHY_CLK_FREQ)
49#define CONFIG_PHY_CLK_FREQ 0
50#endif
51
wdenkaffae2b2002-08-17 09:36:01 +000052/***********************************************************/
Stefan Roese0c7ffc02005-08-16 18:18:00 +020053/* Dump out to the screen PHY regs */
wdenkaffae2b2002-08-17 09:36:01 +000054/***********************************************************/
55
Marian Balakowiczaab8c492005-10-28 22:30:33 +020056void miiphy_dump (char *devname, unsigned char addr)
wdenkaffae2b2002-08-17 09:36:01 +000057{
58 unsigned long i;
59 unsigned short data;
60
wdenkaffae2b2002-08-17 09:36:01 +000061 for (i = 0; i < 0x1A; i++) {
Marian Balakowiczaab8c492005-10-28 22:30:33 +020062 if (miiphy_read (devname, addr, i, &data)) {
wdenkaffae2b2002-08-17 09:36:01 +000063 printf ("read error for reg %lx\n", i);
64 return;
65 }
66 printf ("Phy reg %lx ==> %4x\n", i, data);
67
68 /* jump to the next set of regs */
69 if (i == 0x07)
70 i = 0x0f;
71
Stefan Roese0c7ffc02005-08-16 18:18:00 +020072 } /* end for loop */
73} /* end dump */
wdenkaffae2b2002-08-17 09:36:01 +000074
wdenkaffae2b2002-08-17 09:36:01 +000075/***********************************************************/
Stefan Roese0c7ffc02005-08-16 18:18:00 +020076/* (Re)start autonegotiation */
wdenkaffae2b2002-08-17 09:36:01 +000077/***********************************************************/
Marian Balakowiczaab8c492005-10-28 22:30:33 +020078int phy_setup_aneg (char *devname, unsigned char addr)
Stefan Roese0c7ffc02005-08-16 18:18:00 +020079{
Larry Johnson50325a02007-12-27 10:50:55 -050080 u16 bmcr;
81
82#if defined(CONFIG_PHY_DYNAMIC_ANEG)
83 /*
84 * Set up advertisement based on capablilities reported by the PHY.
85 * This should work for both copper and fiber.
86 */
87 u16 bmsr;
88#if defined(CONFIG_PHY_GIGE)
89 u16 exsr = 0x0000;
90#endif
91
Mike Frysingerd63ee712010-12-23 15:40:12 -050092 miiphy_read (devname, addr, MII_BMSR, &bmsr);
Larry Johnson50325a02007-12-27 10:50:55 -050093
94#if defined(CONFIG_PHY_GIGE)
Mike Frysingerd63ee712010-12-23 15:40:12 -050095 if (bmsr & BMSR_ESTATEN)
96 miiphy_read (devname, addr, MII_ESTATUS, &exsr);
Stefan Roese0c7ffc02005-08-16 18:18:00 +020097
Mike Frysingerd63ee712010-12-23 15:40:12 -050098 if (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)) {
Larry Johnson50325a02007-12-27 10:50:55 -050099 /* 1000BASE-X */
100 u16 anar = 0x0000;
101
Mike Frysingerd63ee712010-12-23 15:40:12 -0500102 if (exsr & ESTATUS_1000XF)
103 anar |= ADVERTISE_1000XFULL);
Larry Johnson50325a02007-12-27 10:50:55 -0500104
Mike Frysingerd63ee712010-12-23 15:40:12 -0500105 if (exsr & ESTATUS_1000XH)
106 anar |= ADVERTISE_1000XHALF;
Larry Johnson50325a02007-12-27 10:50:55 -0500107
Mike Frysingerd63ee712010-12-23 15:40:12 -0500108 miiphy_write (devname, addr, MII_ADVERTISE, anar);
Larry Johnson50325a02007-12-27 10:50:55 -0500109 } else
110#endif
111 {
112 u16 anar, btcr;
113
Mike Frysingerd63ee712010-12-23 15:40:12 -0500114 miiphy_read (devname, addr, MII_ADVERTISE, &anar);
115 anar &= ~(0x5000 | LPA_100BASE4 | LPA_100FULL |
116 LPA_100HALF | LPA_10FULL | LPA_10HALF);
Larry Johnson50325a02007-12-27 10:50:55 -0500117
Mike Frysingerd63ee712010-12-23 15:40:12 -0500118 miiphy_read (devname, addr, MII_CTRL1000, &btcr);
Larry Johnson50325a02007-12-27 10:50:55 -0500119 btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD);
120
Mike Frysingerd63ee712010-12-23 15:40:12 -0500121 if (bmsr & BMSR_100BASE4)
122 anar |= LPA_100BASE4;
Larry Johnson50325a02007-12-27 10:50:55 -0500123
Mike Frysingerd63ee712010-12-23 15:40:12 -0500124 if (bmsr & BMSR_100FULL)
125 anar |= LPA_100FULL;
Larry Johnson50325a02007-12-27 10:50:55 -0500126
Mike Frysingerd63ee712010-12-23 15:40:12 -0500127 if (bmsr & BMSR_100HALF)
128 anar |= LPA_100HALF;
Larry Johnson50325a02007-12-27 10:50:55 -0500129
Mike Frysingerd63ee712010-12-23 15:40:12 -0500130 if (bmsr & BMSR_10FULL)
131 anar |= LPA_10FULL;
Larry Johnson50325a02007-12-27 10:50:55 -0500132
Mike Frysingerd63ee712010-12-23 15:40:12 -0500133 if (bmsr & BMSR_10HALF)
134 anar |= LPA_10HALF;
Larry Johnson50325a02007-12-27 10:50:55 -0500135
Mike Frysingerd63ee712010-12-23 15:40:12 -0500136 miiphy_write (devname, addr, MII_ADVERTISE, anar);
Larry Johnson50325a02007-12-27 10:50:55 -0500137
138#if defined(CONFIG_PHY_GIGE)
Mike Frysingerd63ee712010-12-23 15:40:12 -0500139 if (exsr & ESTATUS_1000_TFULL)
Larry Johnson50325a02007-12-27 10:50:55 -0500140 btcr |= PHY_1000BTCR_1000FD;
141
Mike Frysingerd63ee712010-12-23 15:40:12 -0500142 if (exsr & ESTATUS_1000_THALF)
Larry Johnson50325a02007-12-27 10:50:55 -0500143 btcr |= PHY_1000BTCR_1000HD;
144
Mike Frysingerd63ee712010-12-23 15:40:12 -0500145 miiphy_write (devname, addr, MII_CTRL1000, btcr);
Larry Johnson50325a02007-12-27 10:50:55 -0500146#endif
147 }
148
149#else /* defined(CONFIG_PHY_DYNAMIC_ANEG) */
150 /*
151 * Set up standard advertisement
152 */
153 u16 adv;
154
Mike Frysingerd63ee712010-12-23 15:40:12 -0500155 miiphy_read (devname, addr, MII_ADVERTISE, &adv);
156 adv |= (LPA_LPACK | LPA_100FULL | LPA_100HALF |
157 LPA_10FULL | LPA_10HALF);
158 miiphy_write (devname, addr, MII_ADVERTISE, adv);
wdenkaffae2b2002-08-17 09:36:01 +0000159
Mike Frysingerd63ee712010-12-23 15:40:12 -0500160 miiphy_read (devname, addr, MII_CTRL1000, &adv);
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200161 adv |= (0x0300);
Mike Frysingerd63ee712010-12-23 15:40:12 -0500162 miiphy_write (devname, addr, MII_CTRL1000, adv);
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200163
Larry Johnson50325a02007-12-27 10:50:55 -0500164#endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */
165
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200166 /* Start/Restart aneg */
Mike Frysingerd63ee712010-12-23 15:40:12 -0500167 miiphy_read (devname, addr, MII_BMCR, &bmcr);
168 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
169 miiphy_write (devname, addr, MII_BMCR, bmcr);
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200170
171 return 0;
172}
173
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200174/***********************************************************/
175/* read a phy reg and return the value with a rc */
176/***********************************************************/
Stefan Roese8b231b22008-02-19 21:58:25 +0100177/* AMCC_TODO:
178 * Find out of the choice for the emac for MDIO is from the bridges,
179 * i.e. ZMII or RGMII as approporiate. If the bridges are not used
180 * to determine the emac for MDIO, then is the SDR0_ETH_CFG[MDIO_SEL]
181 * used? If so, then this routine below does not apply to the 460EX/GT.
182 *
183 * sr: Currently on 460EX only EMAC0 works with MDIO, so we always
184 * return EMAC0 offset here
Victor Gallardo45a06ff2008-09-04 23:49:36 -0700185 * vg: For 460EX/460GT if internal GPCS PHY address is specified
186 * return appropriate EMAC offset
Stefan Roese8b231b22008-02-19 21:58:25 +0100187 */
Victor Gallardo45a06ff2008-09-04 23:49:36 -0700188unsigned int miiphy_getemac_offset(u8 addr)
wdenkaffae2b2002-08-17 09:36:01 +0000189{
Stefan Roese8b231b22008-02-19 21:58:25 +0100190#if (defined(CONFIG_440) && \
191 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
192 !defined(CONFIG_460EX) && !defined(CONFIG_460GT)) && \
193 defined(CONFIG_NET_MULTI)
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200194 unsigned long zmii;
195 unsigned long eoffset;
196
197 /* Need to find out which mdi port we're using */
Niklaus Giger728bd0a2009-10-04 20:04:20 +0200198 zmii = in_be32((void *)ZMII0_FER);
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200199
Larry Johnson50325a02007-12-27 10:50:55 -0500200 if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0)))
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200201 /* using port 0 */
202 eoffset = 0;
Larry Johnson50325a02007-12-27 10:50:55 -0500203
204 else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1)))
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200205 /* using port 1 */
206 eoffset = 0x100;
Larry Johnson50325a02007-12-27 10:50:55 -0500207
208 else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2)))
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200209 /* using port 2 */
210 eoffset = 0x400;
Larry Johnson50325a02007-12-27 10:50:55 -0500211
212 else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3)))
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200213 /* using port 3 */
214 eoffset = 0x600;
Larry Johnson50325a02007-12-27 10:50:55 -0500215
216 else {
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200217 /* None of the mdi ports are enabled! */
218 /* enable port 0 */
219 zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
Niklaus Giger728bd0a2009-10-04 20:04:20 +0200220 out_be32((void *)ZMII0_FER, zmii);
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200221 eoffset = 0;
222 /* need to soft reset port 0 */
Niklaus Giger728bd0a2009-10-04 20:04:20 +0200223 zmii = in_be32((void *)EMAC0_MR0);
224 zmii |= EMAC_MR0_SRST;
225 out_be32((void *)EMAC0_MR0, zmii);
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200226 }
227
228 return (eoffset);
229#else
Stefan Roese153b3e22007-10-05 17:10:59 +0200230
231#if defined(CONFIG_NET_MULTI) && defined(CONFIG_405EX)
232 unsigned long rgmii;
233 int devnum = 1;
234
Stefan Roese697100952007-10-23 14:03:17 +0200235 rgmii = in_be32((void *)RGMII_FER);
Stefan Roese153b3e22007-10-05 17:10:59 +0200236 if (rgmii & (1 << (19 - devnum)))
237 return 0x100;
238#endif
239
Victor Gallardo45a06ff2008-09-04 23:49:36 -0700240#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
Victor Gallardo45a06ff2008-09-04 23:49:36 -0700241 u32 eoffset = 0;
242
243 switch (addr) {
244#if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR)
245 case CONFIG_GPCS_PHY1_ADDR:
Niklaus Giger728bd0a2009-10-04 20:04:20 +0200246 if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x100)))
Victor Gallardo45a06ff2008-09-04 23:49:36 -0700247 eoffset = 0x100;
248 break;
249#endif
250#if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR)
251 case CONFIG_GPCS_PHY2_ADDR:
Niklaus Giger728bd0a2009-10-04 20:04:20 +0200252 if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x300)))
Victor Gallardo45a06ff2008-09-04 23:49:36 -0700253 eoffset = 0x300;
254 break;
255#endif
256#if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR)
257 case CONFIG_GPCS_PHY3_ADDR:
Niklaus Giger728bd0a2009-10-04 20:04:20 +0200258 if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x400)))
Victor Gallardo45a06ff2008-09-04 23:49:36 -0700259 eoffset = 0x400;
260 break;
261#endif
262 default:
263 eoffset = 0;
264 break;
265 }
266 return eoffset;
267#endif
268
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200269 return 0;
270#endif
271}
272
Stefan Roese8b231b22008-02-19 21:58:25 +0100273static int emac_miiphy_wait(u32 emac_reg)
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200274{
Stefan Roese8b231b22008-02-19 21:58:25 +0100275 u32 sta_reg;
276 int i;
wdenkaffae2b2002-08-17 09:36:01 +0000277
Stefan Roese8b231b22008-02-19 21:58:25 +0100278 /* wait for completion */
wdenkaffae2b2002-08-17 09:36:01 +0000279 i = 0;
Stefan Roese8b231b22008-02-19 21:58:25 +0100280 do {
Niklaus Giger728bd0a2009-10-04 20:04:20 +0200281 sta_reg = in_be32((void *)EMAC0_STACR + emac_reg);
Stefan Roese8b231b22008-02-19 21:58:25 +0100282 if (i++ > 5) {
Niklaus Giger728bd0a2009-10-04 20:04:20 +0200283 debug("%s [%d]: Timeout! EMAC0_STACR=0x%0x\n", __func__,
Stefan Roese8b231b22008-02-19 21:58:25 +0100284 __LINE__, sta_reg);
wdenkaffae2b2002-08-17 09:36:01 +0000285 return -1;
286 }
Stefan Roese8b231b22008-02-19 21:58:25 +0100287 udelay(10);
288 } while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK);
289
290 return 0;
291}
292
293static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
294{
295 u32 emac_reg;
296 u32 sta_reg;
297
Victor Gallardo45a06ff2008-09-04 23:49:36 -0700298 emac_reg = miiphy_getemac_offset(addr);
Stefan Roese8b231b22008-02-19 21:58:25 +0100299
300 /* wait for completion */
301 if (emac_miiphy_wait(emac_reg) != 0)
302 return -1;
303
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200304 sta_reg = reg; /* reg address */
Stefan Roese8b231b22008-02-19 21:58:25 +0100305
Wolfgang Denkaf0501a2008-10-19 02:35:50 +0200306 /* set clock (50MHz) and read flags */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200307#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
Stefan Roese153b3e22007-10-05 17:10:59 +0200308 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese8b231b22008-02-19 21:58:25 +0100309 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roese153b3e22007-10-05 17:10:59 +0200310 defined(CONFIG_405EX)
Larry Johnson50325a02007-12-27 10:50:55 -0500311#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
Stefan Roese8b231b22008-02-19 21:58:25 +0100312 sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | cmd;
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200313#else
Stefan Roese8b231b22008-02-19 21:58:25 +0100314 sta_reg |= cmd;
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200315#endif
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200316#else
Stefan Roese8b231b22008-02-19 21:58:25 +0100317 sta_reg = (sta_reg | cmd) & ~EMAC_STACR_CLK_100MHZ;
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200318#endif
319
Stefan Roese8b231b22008-02-19 21:58:25 +0100320 /* Some boards (mainly 405EP based) define the PHY clock freqency fixed */
wdenk232fe0b2003-09-02 22:48:03 +0000321 sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
Stefan Roese8b231b22008-02-19 21:58:25 +0100322 sta_reg = sta_reg | ((u32)addr << 5); /* Phy address */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200323 sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
Stefan Roese8b231b22008-02-19 21:58:25 +0100324 if (cmd == EMAC_STACR_WRITE)
325 memcpy(&sta_reg, &value, 2); /* put in data */
326
Niklaus Giger728bd0a2009-10-04 20:04:20 +0200327 out_be32((void *)EMAC0_STACR + emac_reg, sta_reg);
Stefan Roese8b231b22008-02-19 21:58:25 +0100328 debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
wdenkaffae2b2002-08-17 09:36:01 +0000329
Stefan Roese8b231b22008-02-19 21:58:25 +0100330 /* wait for completion */
331 if (emac_miiphy_wait(emac_reg) != 0)
332 return -1;
Larry Johnson50325a02007-12-27 10:50:55 -0500333
Stefan Roese8b231b22008-02-19 21:58:25 +0100334 debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
Larry Johnson50325a02007-12-27 10:50:55 -0500335 if ((sta_reg & EMAC_STACR_PHYE) != 0)
wdenkaffae2b2002-08-17 09:36:01 +0000336 return -1;
wdenkaffae2b2002-08-17 09:36:01 +0000337
wdenkaffae2b2002-08-17 09:36:01 +0000338 return 0;
Stefan Roese8b231b22008-02-19 21:58:25 +0100339}
wdenkaffae2b2002-08-17 09:36:01 +0000340
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400341int emac4xx_miiphy_read (const char *devname, unsigned char addr, unsigned char reg,
Stefan Roese8b231b22008-02-19 21:58:25 +0100342 unsigned short *value)
wdenkaffae2b2002-08-17 09:36:01 +0000343{
Stefan Roese8b231b22008-02-19 21:58:25 +0100344 unsigned long sta_reg;
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200345 unsigned long emac_reg;
wdenkaffae2b2002-08-17 09:36:01 +0000346
Victor Gallardo45a06ff2008-09-04 23:49:36 -0700347 emac_reg = miiphy_getemac_offset(addr);
wdenkaffae2b2002-08-17 09:36:01 +0000348
Stefan Roese8b231b22008-02-19 21:58:25 +0100349 if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0)
350 return -1;
wdenkaffae2b2002-08-17 09:36:01 +0000351
Niklaus Giger728bd0a2009-10-04 20:04:20 +0200352 sta_reg = in_be32((void *)EMAC0_STACR + emac_reg);
Stefan Roese1fc08dd2009-09-07 10:52:24 +0200353 *value = sta_reg >> 16;
Larry Johnson50325a02007-12-27 10:50:55 -0500354
wdenkaffae2b2002-08-17 09:36:01 +0000355 return 0;
Stefan Roese8b231b22008-02-19 21:58:25 +0100356}
wdenkaffae2b2002-08-17 09:36:01 +0000357
Stefan Roese8b231b22008-02-19 21:58:25 +0100358/***********************************************************/
359/* write a phy reg and return the value with a rc */
360/***********************************************************/
361
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400362int emac4xx_miiphy_write (const char *devname, unsigned char addr, unsigned char reg,
Stefan Roese8b231b22008-02-19 21:58:25 +0100363 unsigned short value)
364{
365 return emac_miiphy_command(addr, reg, EMAC_STACR_WRITE, value);
366}