| Tom Warren | b7ea6d1 | 2014-01-24 12:46:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010-2013 |
| 3 | * NVIDIA Corporation <www.nvidia.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | /* Tegra124 clock control definitions */ |
| 9 | |
| 10 | #ifndef _TEGRA124_CLOCK_H_ |
| 11 | #define _TEGRA124_CLOCK_H_ |
| 12 | |
| 13 | #include <asm/arch-tegra/clock.h> |
| 14 | |
| 15 | /* CLK_RST_CONTROLLER_OSC_CTRL_0 */ |
| 16 | #define OSC_FREQ_SHIFT 28 |
| 17 | #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) |
| 18 | |
| Thierry Reding | 4bf9869 | 2014-12-09 22:25:06 -0700 | [diff] [blame] | 19 | int tegra_plle_enable(void); |
| 20 | |
| Tom Warren | b7ea6d1 | 2014-01-24 12:46:13 -0700 | [diff] [blame] | 21 | #endif /* _TEGRA124_CLOCK_H_ */ |