blob: 3a92f5a7b47e2ca5067e3b1a536d562eefeca9e4 [file] [log] [blame]
Wang Huan8ce6bec2014-09-05 13:52:34 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __FSL_SERDES_H
8#define __FSL_SERDES_H
9
10#include <config.h>
11
12enum srds_prtcl {
13 NONE = 0,
14 PCIE1,
15 PCIE2,
16 SATA1,
17 SGMII_TSEC1,
18 SGMII_TSEC2,
19};
20
21enum srds {
22 FSL_SRDS_1 = 0,
23 FSL_SRDS_2 = 1,
24};
25
26int is_serdes_configured(enum srds_prtcl device);
27void fsl_serdes_init(void);
28const char *serdes_clock_to_string(u32 clock);
29
30int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
31enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
32
33#endif /* __FSL_SERDES_H */