| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Marcel Ziswiler | d2b64bd | 2017-04-01 15:43:16 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2012-2016 Toradex, Inc. |
| Marcel Ziswiler | d2b64bd | 2017-04-01 15:43:16 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | /* AS3722-PMIC-specific early init regs */ |
| 7 | |
| 8 | #define AS3722_I2C_ADDR 0x80 |
| 9 | |
| 10 | #define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */ |
| 11 | #define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */ |
| 12 | #define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */ |
| 13 | #define AS3722_SDCONTROL_REG 0x4D |
| 14 | |
| 15 | #define AS3722_LDO1VOLTAGE_REG 0x11 /* VDD_SDMMC1 */ |
| 16 | #define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */ |
| 17 | #define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC3 */ |
| 18 | #define AS3722_LDCONTROL_REG 0x4E |
| 19 | |
| 20 | #define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG) |
| 21 | #define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG) |
| 22 | |
| 23 | #define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG) |
| 24 | #define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG) |
| 25 | |
| 26 | #define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG) |
| 27 | #define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG) |
| 28 | |
| 29 | #define AS3722_LDO1CONTROL_DATA (0x0200 | AS3722_LDCONTROL_REG) |
| 30 | #define AS3722_LDO1VOLTAGE_DATA (0x7F00 | AS3722_LDO1VOLTAGE_REG) |
| 31 | |
| 32 | #define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG) |
| 33 | #define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG) |
| 34 | |
| 35 | #define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG) |
| 36 | #define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG) |
| 37 | |
| 38 | #define I2C_SEND_2_BYTES 0x0A02 |
| 39 | |
| 40 | void pmic_enable_cpu_vdd(void); |