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wdenkedc48b62002-09-08 17:56:50 +00001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkedc48b62002-09-08 17:56:50 +00006 */
7
8/* for now: just dummy functions to satisfy the linker */
9
wdenkf8062712005-01-09 23:16:25 +000010#include <common.h>
Thierry Redingc97d9742014-12-09 22:25:22 -070011#include <malloc.h>
wdenkf8062712005-01-09 23:16:25 +000012
Jeroen Hofsteed7460772014-06-23 22:07:04 +020013__weak void flush_cache(unsigned long start, unsigned long size)
wdenkedc48b62002-09-08 17:56:50 +000014{
Masahiro Yamadaa8b4c8c2014-11-06 14:59:37 +090015#if defined(CONFIG_CPU_ARM1136)
wdenkf8062712005-01-09 23:16:25 +000016
Albert ARIBAUD7a6fd042014-04-15 16:13:47 +020017#if !defined(CONFIG_SYS_ICACHE_OFF)
18 asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */
wdenkf8062712005-01-09 23:16:25 +000019#endif
Albert ARIBAUD7a6fd042014-04-15 16:13:47 +020020
21#if !defined(CONFIG_SYS_DCACHE_OFF)
22 asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */
23#endif
24
Masahiro Yamadaa8b4c8c2014-11-06 14:59:37 +090025#endif /* CONFIG_CPU_ARM1136 */
Albert ARIBAUD7a6fd042014-04-15 16:13:47 +020026
Masahiro Yamada4fb5d072014-11-06 14:59:36 +090027#ifdef CONFIG_CPU_ARM926EJS
Heiko Schocher54433092010-09-17 13:10:30 +020028 /* test and clean, page 2-23 of arm926ejs manual */
29 asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
30 /* disable write buffer as well (page 2-22) */
31 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
Masahiro Yamada4fb5d072014-11-06 14:59:36 +090032#endif /* CONFIG_CPU_ARM926EJS */
wdenkedc48b62002-09-08 17:56:50 +000033 return;
34}
Aneesh V3bda3772011-06-16 23:30:50 +000035
36/*
37 * Default implementation:
38 * do a range flush for the entire range
39 */
Jeroen Hofsteed7460772014-06-23 22:07:04 +020040__weak void flush_dcache_all(void)
Aneesh V3bda3772011-06-16 23:30:50 +000041{
42 flush_cache(0, ~0);
43}
Aneesh Vfffbb972011-08-16 04:33:05 +000044
45/*
46 * Default implementation of enable_caches()
47 * Real implementation should be in platform code
48 */
Jeroen Hofsteed7460772014-06-23 22:07:04 +020049__weak void enable_caches(void)
Aneesh Vfffbb972011-08-16 04:33:05 +000050{
51 puts("WARNING: Caches not enabled\n");
52}
Thierry Redingc97d9742014-12-09 22:25:22 -070053
54#ifdef CONFIG_SYS_NONCACHED_MEMORY
55/*
56 * Reserve one MMU section worth of address space below the malloc() area that
57 * will be mapped uncached.
58 */
59static unsigned long noncached_start;
60static unsigned long noncached_end;
61static unsigned long noncached_next;
62
63void noncached_init(void)
64{
65 phys_addr_t start, end;
66 size_t size;
67
68 end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
69 size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
70 start = end - size;
71
72 debug("mapping memory %pa-%pa non-cached\n", &start, &end);
73
74 noncached_start = start;
75 noncached_end = end;
76 noncached_next = start;
77
78#ifndef CONFIG_SYS_DCACHE_OFF
79 mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
80#endif
81}
82
83phys_addr_t noncached_alloc(size_t size, size_t align)
84{
85 phys_addr_t next = ALIGN(noncached_next, align);
86
87 if (next >= noncached_end || (noncached_end - next) < size)
88 return 0;
89
90 debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
91 noncached_next = next + size;
92
93 return next;
94}
95#endif /* CONFIG_SYS_NONCACHED_MEMORY */