wdenk | edc48b6 | 2002-09-08 17:56:50 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | edc48b6 | 2002-09-08 17:56:50 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* for now: just dummy functions to satisfy the linker */ |
| 9 | |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 10 | #include <common.h> |
Thierry Reding | c97d974 | 2014-12-09 22:25:22 -0700 | [diff] [blame] | 11 | #include <malloc.h> |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 12 | |
Jeroen Hofstee | d746077 | 2014-06-23 22:07:04 +0200 | [diff] [blame] | 13 | __weak void flush_cache(unsigned long start, unsigned long size) |
wdenk | edc48b6 | 2002-09-08 17:56:50 +0000 | [diff] [blame] | 14 | { |
Masahiro Yamada | a8b4c8c | 2014-11-06 14:59:37 +0900 | [diff] [blame] | 15 | #if defined(CONFIG_CPU_ARM1136) |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 16 | |
Albert ARIBAUD | 7a6fd04 | 2014-04-15 16:13:47 +0200 | [diff] [blame] | 17 | #if !defined(CONFIG_SYS_ICACHE_OFF) |
| 18 | asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */ |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 19 | #endif |
Albert ARIBAUD | 7a6fd04 | 2014-04-15 16:13:47 +0200 | [diff] [blame] | 20 | |
| 21 | #if !defined(CONFIG_SYS_DCACHE_OFF) |
| 22 | asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */ |
| 23 | #endif |
| 24 | |
Masahiro Yamada | a8b4c8c | 2014-11-06 14:59:37 +0900 | [diff] [blame] | 25 | #endif /* CONFIG_CPU_ARM1136 */ |
Albert ARIBAUD | 7a6fd04 | 2014-04-15 16:13:47 +0200 | [diff] [blame] | 26 | |
Masahiro Yamada | 4fb5d07 | 2014-11-06 14:59:36 +0900 | [diff] [blame] | 27 | #ifdef CONFIG_CPU_ARM926EJS |
Heiko Schocher | 5443309 | 2010-09-17 13:10:30 +0200 | [diff] [blame] | 28 | /* test and clean, page 2-23 of arm926ejs manual */ |
| 29 | asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); |
| 30 | /* disable write buffer as well (page 2-22) */ |
| 31 | asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); |
Masahiro Yamada | 4fb5d07 | 2014-11-06 14:59:36 +0900 | [diff] [blame] | 32 | #endif /* CONFIG_CPU_ARM926EJS */ |
wdenk | edc48b6 | 2002-09-08 17:56:50 +0000 | [diff] [blame] | 33 | return; |
| 34 | } |
Aneesh V | 3bda377 | 2011-06-16 23:30:50 +0000 | [diff] [blame] | 35 | |
| 36 | /* |
| 37 | * Default implementation: |
| 38 | * do a range flush for the entire range |
| 39 | */ |
Jeroen Hofstee | d746077 | 2014-06-23 22:07:04 +0200 | [diff] [blame] | 40 | __weak void flush_dcache_all(void) |
Aneesh V | 3bda377 | 2011-06-16 23:30:50 +0000 | [diff] [blame] | 41 | { |
| 42 | flush_cache(0, ~0); |
| 43 | } |
Aneesh V | fffbb97 | 2011-08-16 04:33:05 +0000 | [diff] [blame] | 44 | |
| 45 | /* |
| 46 | * Default implementation of enable_caches() |
| 47 | * Real implementation should be in platform code |
| 48 | */ |
Jeroen Hofstee | d746077 | 2014-06-23 22:07:04 +0200 | [diff] [blame] | 49 | __weak void enable_caches(void) |
Aneesh V | fffbb97 | 2011-08-16 04:33:05 +0000 | [diff] [blame] | 50 | { |
| 51 | puts("WARNING: Caches not enabled\n"); |
| 52 | } |
Thierry Reding | c97d974 | 2014-12-09 22:25:22 -0700 | [diff] [blame] | 53 | |
| 54 | #ifdef CONFIG_SYS_NONCACHED_MEMORY |
| 55 | /* |
| 56 | * Reserve one MMU section worth of address space below the malloc() area that |
| 57 | * will be mapped uncached. |
| 58 | */ |
| 59 | static unsigned long noncached_start; |
| 60 | static unsigned long noncached_end; |
| 61 | static unsigned long noncached_next; |
| 62 | |
| 63 | void noncached_init(void) |
| 64 | { |
| 65 | phys_addr_t start, end; |
| 66 | size_t size; |
| 67 | |
| 68 | end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE; |
| 69 | size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE); |
| 70 | start = end - size; |
| 71 | |
| 72 | debug("mapping memory %pa-%pa non-cached\n", &start, &end); |
| 73 | |
| 74 | noncached_start = start; |
| 75 | noncached_end = end; |
| 76 | noncached_next = start; |
| 77 | |
| 78 | #ifndef CONFIG_SYS_DCACHE_OFF |
| 79 | mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF); |
| 80 | #endif |
| 81 | } |
| 82 | |
| 83 | phys_addr_t noncached_alloc(size_t size, size_t align) |
| 84 | { |
| 85 | phys_addr_t next = ALIGN(noncached_next, align); |
| 86 | |
| 87 | if (next >= noncached_end || (noncached_end - next) < size) |
| 88 | return 0; |
| 89 | |
| 90 | debug("allocated %zu bytes of uncached memory @%pa\n", size, &next); |
| 91 | noncached_next = next + size; |
| 92 | |
| 93 | return next; |
| 94 | } |
| 95 | #endif /* CONFIG_SYS_NONCACHED_MEMORY */ |