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git01.mediatek.com / filogic / uboot / d5c48aedc924b60ba3c39e0b1dcf7360fd96090d / . / board / ti / tnetv107xevm / sdb_board.c
blob: a84ec84baeb0f803f7746107f194435135280691 [file] [log] [blame]
Cyril Chemparathy3d138062010-06-07 14:13:36 -0400[diff] [blame]1/*
2 * TNETV107X-EVM: Board initialization
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Cyril Chemparathy3d138062010-06-07 14:13:36 -0400[diff] [blame]5 */
6
7#include <common.h>
8#include <miiphy.h>
9#include <linux/mtd/nand.h>
10#include <asm/arch/hardware.h>
11#include <asm/arch/clock.h>
12#include <asm/io.h>
13#include <asm/mach-types.h>
Khoronzhuk, Ivan753a00a2014-06-07 04:22:52 +0300[diff] [blame]14#include <asm/ti-common/davinci_nand.h>
Cyril Chemparathy3d138062010-06-07 14:13:36 -0400[diff] [blame]15#include <asm/arch/mux.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
20 { /* CS0 */
21 .mode = ASYNC_EMIF_MODE_NAND,
22 .wr_setup = 5,
23 .wr_strobe = 5,
24 .wr_hold = 2,
25 .rd_setup = 5,
26 .rd_strobe = 5,
27 .rd_hold = 2,
28 .turn_around = 5,
29 .width = ASYNC_EMIF_8,
30 },
31 { /* CS1 */
32 .mode = ASYNC_EMIF_MODE_NOR,
33 .wr_setup = 2,
34 .wr_strobe = 27,
35 .wr_hold = 4,
36 .rd_setup = 2,
37 .rd_strobe = 27,
38 .rd_hold = 4,
39 .turn_around = 2,
40 .width = ASYNC_EMIF_PRESERVE,
41 },
42 { /* CS2 */
43 .mode = ASYNC_EMIF_MODE_NOR,
44 .wr_setup = 2,
45 .wr_strobe = 27,
46 .wr_hold = 4,
47 .rd_setup = 2,
48 .rd_strobe = 27,
49 .rd_hold = 4,
50 .turn_around = 2,
51 .width = ASYNC_EMIF_PRESERVE,
52 },
53 { /* CS3 */
54 .mode = ASYNC_EMIF_MODE_NOR,
55 .wr_setup = 1,
56 .wr_strobe = 90,
57 .wr_hold = 3,
58 .rd_setup = 1,
59 .rd_strobe = 26,
60 .rd_hold = 3,
61 .turn_around = 1,
62 .width = ASYNC_EMIF_8,
63 },
64};
65
66static struct pll_init_data pll_config[] = {
67 {
68 .pll = ETH_PLL,
69 .internal_osc = 1,
70 .pll_freq = 500000000,
71 .div_freq = {
72 5000000, 50000000, 125000000, 250000000, 25000000,
73 },
74 },
75};
76
77static const short sdio1_pins[] = {
78 TNETV107X_PIN_SDIO1_CLK_1, TNETV107X_PIN_SDIO1_CMD_1,
79 TNETV107X_PIN_SDIO1_DATA0_1, TNETV107X_PIN_SDIO1_DATA1_1,
80 TNETV107X_PIN_SDIO1_DATA2_1, TNETV107X_PIN_SDIO1_DATA3_1,
81 -1
82};
83
84static const short uart1_pins[] = {
85 TNETV107X_PIN_UART1_RD, TNETV107X_PIN_UART1_TD, -1
86};
87
88static const short ssp_pins[] = {
89 TNETV107X_PIN_SSP0_0, TNETV107X_PIN_SSP0_1, TNETV107X_PIN_SSP0_2,
90 TNETV107X_PIN_SSP1_0, TNETV107X_PIN_SSP1_1, TNETV107X_PIN_SSP1_2,
91 TNETV107X_PIN_SSP1_3, -1
92};
93
94int board_init(void)
95{
96#ifndef CONFIG_USE_IRQ
97 __raw_writel(0, INTC_GLB_EN); /* Global disable */
98 __raw_writel(0, INTC_HINT_EN); /* Disable host ints */
99 __raw_writel(0, INTC_EN_CLR0 + 0); /* Clear enable */
100 __raw_writel(0, INTC_EN_CLR0 + 4); /* Clear enable */
101 __raw_writel(0, INTC_EN_CLR0 + 8); /* Clear enable */
102#endif
103
104 gd->bd->bi_arch_number = MACH_TYPE_TNETV107X;
105 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
106
107 init_plls(ARRAY_SIZE(pll_config), pll_config);
108
109 init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
110
111 mux_select_pin(TNETV107X_PIN_ASR_CS3);
112 mux_select_pins(sdio1_pins);
113 mux_select_pins(uart1_pins);
114 mux_select_pins(ssp_pins);
115
116 return 0;
117}
118
119int dram_init(void)
120{
121 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
122 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
123
124 return 0;
125}
126
127#ifdef CONFIG_NAND_DAVINCI
128int board_nand_init(struct nand_chip *nand)
129{
130 davinci_nand_init(nand);
131
132 return 0;
133}
134#endif