blob: 9a7669c940b4c45c266fbad44b1590e3d60d9a56 [file] [log] [blame]
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +00001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2020 Hitachi Power Grids. All rights reserved.
4 */
5
6#ifndef __CONFIG_PG_WCOM_SELI8_H
7#define __CONFIG_PG_WCOM_SELI8_H
8
9#define CONFIG_HOSTNAME "SELI8"
10
11#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
12#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
13
14/* PAXK FPGA Definitions */
15#define CONFIG_SYS_CSPR3_EXT (0x00)
16#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \
17 CSPR_PORT_SIZE_8 | \
18 CSPR_MSEL_GPCM | \
19 CSPR_V)
20#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
21#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
22 CSOR_GPCM_TRHZ_40)
23#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
24 FTIM0_GPCM_TEADC(0x7) | \
25 FTIM0_GPCM_TEAHC(0x2))
26#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
27 FTIM1_GPCM_TRAD(0x12))
28#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
29 FTIM2_GPCM_TCH(0x1) | \
30 FTIM2_GPCM_TWP(0x12))
31#define CONFIG_SYS_CS3_FTIM3 0x04000000
32
33/* PRST */
34#define KM_LIU_RST 0
35#define KM_PAXK_RST 1
36#define KM_DBG_ETH_RST 15
37
38/* QRIO GPIOs used for deblocking */
39#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
40#define KM_I2C_DEBLOCK_SCL 20
41#define KM_I2C_DEBLOCK_SDA 21
42
43#include "km/pg-wcom-ls102xa.h"
44
45#endif /* __CONFIG_PG_WCOM_SELI8_H */