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git01.mediatek.com / filogic / uboot / d5b477f47b30cd276a77f92686ec7f0fcaba2c2a / . / arch / powerpc / include / asm / global_data.h
blob: f7860122a00b903765850205f1aaf4dad156173c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]2/*
Wolfgang Denkf710efd2010-07-24 20:22:02 +0200[diff] [blame]3 * (C) Copyright 2002-2010
Yangbo Luff98fde2020-06-17 18:08:57 +0800[diff] [blame]4 * Copyright 2020 NXP
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]6 */
7
8#ifndef __ASM_GBL_DATA_H
9#define __ASM_GBL_DATA_H
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]10
Tom Rini10599d62023-11-01 12:28:06 -0400[diff] [blame]11#include <linux/types.h>
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]12
Simon Glass3ac47d72012-12-13 20:48:30 +0000[diff] [blame]13/* Architecture-specific global data */
14struct arch_global_data {
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]15#if defined(CONFIG_FSL_ESDHC)
16 u32 sdhc_clk;
Yangbo Lu0fa68762019-12-19 18:59:28 +0800[diff] [blame]17 u32 sdhc_per_clk;
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]18#endif
Christophe Leroyb3510fb2018-03-16 17:20:41 +0100[diff] [blame]19#if defined(CONFIG_MPC8xx)
Christophe Leroy069fa832017-07-06 10:23:22 +0200[diff] [blame]20 unsigned long brg_clk;
21#endif
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]22 /* TODO: sjg@chromium.org: Should these be unslgned long? */
Peter Tyser62e73982009-05-22 17:23:24 -0500[diff] [blame]23#if defined(CONFIG_MPC83xx)
Mario Six7cab1472018-08-06 10:23:36 +0200[diff] [blame]24#ifdef CONFIG_CLK_MPC83XX
25 u32 core_clk;
26#else
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]27 /* There are other clocks in the MPC83XX */
28 u32 csb_clk;
Mario Six9164bdd2019-01-21 09:17:25 +0100[diff] [blame]29# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +0100[diff] [blame]30 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]31 u32 tsec1_clk;
32 u32 tsec2_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]33 u32 usbdr_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]34# endif
Mario Six0344f5e2019-01-21 09:17:27 +0100[diff] [blame]35# if defined(CONFIG_ARCH_MPC834X)
Scott Woodbeb638a2007-04-16 14:34:18 -0500[diff] [blame]36 u32 usbmph_clk;
Mario Six0344f5e2019-01-21 09:17:27 +0100[diff] [blame]37# endif /* CONFIG_ARCH_MPC834X */
Dave Liua46daea2006-11-03 19:33:44 -0600[diff] [blame]38 u32 core_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]39 u32 enc_clk;
40 u32 lbiu_clk;
41 u32 lclk_clk;
Mario Six9164bdd2019-01-21 09:17:25 +0100[diff] [blame]42# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +0100[diff] [blame]43 defined(CONFIG_ARCH_MPC837X)
Dave Liu5245ff52007-09-18 12:36:11 +0800[diff] [blame]44 u32 pciexp1_clk;
45 u32 pciexp2_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]46# endif
Tom Rinid9e6ef52021-05-14 21:34:27 -0400[diff] [blame]47# if defined(CONFIG_ARCH_MPC837X)
Dave Liu5245ff52007-09-18 12:36:11 +0800[diff] [blame]48 u32 sata_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]49# endif
Mario Six84eb4312019-01-21 09:17:28 +0100[diff] [blame]50# if defined(CONFIG_ARCH_MPC8360)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]51 u32 mem_sec_clk;
Mario Six84eb4312019-01-21 09:17:28 +0100[diff] [blame]52# endif /* CONFIG_ARCH_MPC8360 */
Dave Liu5245ff52007-09-18 12:36:11 +0800[diff] [blame]53#endif
Mario Six7cab1472018-08-06 10:23:36 +0200[diff] [blame]54#endif
Simon Glassa8b57392012-12-13 20:48:48 +0000[diff] [blame]55#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
56 u32 lbc_clk;
57 void *cpu;
58#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
Simon Glassc2baaec2012-12-13 20:48:49 +0000[diff] [blame]59#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
60 defined(CONFIG_MPC86xx)
61 u32 i2c1_clk;
62 u32 i2c2_clk;
63#endif
Simon Glass8518b172012-12-13 20:48:50 +0000[diff] [blame]64#if defined(CONFIG_QE)
65 u32 qe_clk;
66 u32 brg_clk;
67 uint mp_alloc_base;
68 uint mp_alloc_top;
69#endif /* CONFIG_QE */
Simon Glassc6622d62012-12-13 20:48:51 +0000[diff] [blame]70#if defined(CONFIG_FSL_LAW)
71 u32 used_laws;
72#endif
Simon Glass0b466582012-12-13 20:48:52 +0000[diff] [blame]73#if defined(CONFIG_E500)
74 u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
75#endif
Simon Glass4d6eaa32012-12-13 20:48:56 +0000[diff] [blame]76 unsigned long reset_status; /* reset status register at boot */
Simon Glass387a1f22012-12-13 20:48:57 +0000[diff] [blame]77#if defined(CONFIG_MPC83xx)
78 unsigned long arbiter_event_attributes;
79 unsigned long arbiter_event_address;
80#endif
Simon Glassf2d9aaf2012-12-13 20:49:02 +0000[diff] [blame]81#ifdef CONFIG_SYS_FPGA_COUNT
82 unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
83#endif
Stefan Roeseb47a63d2015-10-02 08:20:35 +0200[diff] [blame]84#if defined(CONFIG_WD_MAX_RATE)
85 unsigned long long wdt_last; /* trace watch-dog triggering rate */
86#endif
87#if defined(CONFIG_LWMON5)
88 unsigned long kbd_status;
89#endif
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]90};
91
Simon Glass1c62cc22012-12-13 20:49:23 +0000[diff] [blame]92#include <asm-generic/global_data.h>
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]93
Wolfgang Denk69c09642008-02-14 22:43:22 +0100[diff] [blame]94#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]95
96#endif /* __ASM_GBL_DATA_H */