Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / d5aa5058a0191c631027186ad9dda0322cefe5d8 / . / arch / arm / dts / imx8qm-cgtqmx8.dts
blob: 555c357f6f79b3f24ea971d6fae02505f38fc2f4 [file] [log] [blame]
Oliver Grauteaf5e29b2021-05-31 15:50:40 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017 NXP
5 * Copyright 2017 congatec AG
6 * Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
7 */
8
9/dts-v1/;
10
11/* First 128KB is for PSCI ATF. */
12/memreserve/ 0x80000000 0x00020000;
13
14#include "fsl-imx8qm.dtsi"
15
16/ {
17 model = "Congatec QMX8 Qseven series";
18 compatible = "fsl,imx8qm-qmx8", "fsl,imx8qm";
19
20 chosen {
21 bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
22 stdout-path = &lpuart0;
23 };
24
25 regulators {
26 compatible = "simple-bus";
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 reg_usdhc2_vmmc: usdhc2_vmmc {
31 compatible = "regulator-fixed";
32 regulator-name = "sw-3p3-sd1";
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
36 enable-active-high;
37 off-on-delay-us = <3000>;
38 };
39
40 reg_usdhc3_vmmc: usdhc3_vmmc {
41 compatible = "regulator-fixed";
42 regulator-name = "sw-3p3-sd2";
43 regulator-min-microvolt = <3300000>;
44 regulator-max-microvolt = <3300000>;
45 gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
46 enable-active-high;
47 off-on-delay-us = <3000>;
48 };
49 };
50};
51
52&fec1 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_fec1>;
55 phy-mode = "rgmii";
56 phy-handle = <&ethphy0>;
57 fsl,magic-packet;
58 fsl,rgmii_txc_dly;
59 fsl,rgmii_rxc_dly;
60 status = "okay";
61
62 mdio {
63 #address-cells = <1>;
64 #size-cells = <0>;
65
66 ethphy0: ethernet-phy@6 {
67 compatible = "ethernet-phy-ieee802.3-c22";
68 reg = <6>;
69 at803x,eee-disabled;
70 at803x,vddio-1p8v;
71 };
72 };
73};
74
75&gpio2 {
76 status = "okay";
77};
78
79&gpio5 {
80 status = "okay";
81};
82
83&i2c0 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_lpi2c0>;
88 clock-frequency = <100000>;
89 status = "okay";
90
91 rtc_ext: m41t62@68 {
92 compatible = "st,m41t62";
93 reg = <0x68>;
94 };
95};
96
97&i2c1 {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 clock-frequency = <100000>;
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_lpi2c1>;
103 status = "okay";
104
105 wm8904: wm8904@1a {
106 compatible = "wlf,wm8904";
107 reg = <0x1a>;
108
109 clocks = <&clk IMX8QM_AUD_MCLKOUT0>;
110 clock-names = "mclk";
111 wlf,shared-lrclk;
112 /* power-domains = <&pd_mclk_out0>; */
113
114 assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
115 <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
116 <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
117 <&clk IMX8QM_AUD_MCLKOUT0>;
118
119 assigned-clock-rates = <786432000>, <49152000>, <24576000>;
120 };
121};
122
123&iomuxc {
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_hog>;
126
127 imx8qm-qmx8 {
128
129 pinctrl_hog: hoggrp{
130 fsl,pins = <
131 SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 0x00000021
132 SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021
133 SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 0x00000021
134 SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021
135 SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021
136 SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 0x00000021
137 SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021
138 SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 0x00000021
139 SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021
140 >;
141 };
142
143 pinctrl_fec1: fec1grp {
144 fsl,pins = <
145 SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
146 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
147 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
148 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
149 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
150 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
151 SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
152 SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
153 SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
154 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
155 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
156 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
157 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
158 SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
159 >;
160 };
161
162 pinctrl_lpi2c0: lpi2c0grp {
163 fsl,pins = <
164 SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c
165 SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c
166 >;
167 };
168
169 pinctrl_lpi2c1: lpi2c1grp {
170 fsl,pins = <
171 SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c
172 SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c
173 >;
174 };
175
176 pinctrl_lpuart0: lpuart0grp {
177 fsl,pins = <
178 SC_P_UART0_RX_DMA_UART0_RX 0x06000020
179 SC_P_UART0_TX_DMA_UART0_TX 0x06000020
180 >;
181 };
182
183 pinctrl_lpuart1: lpuart1grp {
184 fsl,pins = <
185 SC_P_UART1_RX_DMA_UART1_RX 0x06000020
186 SC_P_UART1_TX_DMA_UART1_TX 0x06000020
187 SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020
188 SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020
189 >;
190 };
191
192 pinctrl_lpuart3: lpuart3grp {
193 fsl,pins = <
194 SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020
195 SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020
196 >;
197 };
198
199 pinctrl_mlb: mlbgrp {
200 fsl,pins = <
201 SC_P_MLB_SIG_CONN_MLB_SIG 0x21
202 SC_P_MLB_CLK_CONN_MLB_CLK 0x21
203 SC_P_MLB_DATA_CONN_MLB_DATA 0x21
204 >;
205 };
206
207 pinctrl_isl29023: isl29023grp {
208 fsl,pins = <
209 SC_P_ADC_IN2_LSIO_GPIO3_IO20 0x00000021
210 >;
211 };
212
213 pinctrl_usdhc1: usdhc1grp {
214 fsl,pins = <
215 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
216 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
217 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
218 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
219 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
220 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
221 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
222 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
223 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
224 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
225 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
226 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
227 >;
228 };
229
230 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
231 fsl,pins = <
232 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
233 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
234 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
235 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
236 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
237 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
238 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
239 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
240 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
241 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
242 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
243 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
244 >;
245 };
246
247 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
248 fsl,pins = <
249 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
250 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
251 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
252 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
253 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
254 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
255 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
256 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
257 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
258 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
259 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
260 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
261 >;
262 };
263
264 pinctrl_usdhc2_gpio: usdhc2grpgpio {
265 fsl,pins = <
266 SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
267 SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
268 SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
269 >;
270 };
271
272 pinctrl_usdhc2: usdhc2grp {
273 fsl,pins = <
274 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
275 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
276 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
277 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
278 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
279 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
280 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
281 >;
282 };
283
284 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
285 fsl,pins = <
286 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
287 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
288 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
289 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
290 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
291 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
292 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
293 >;
294 };
295
296 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
297 fsl,pins = <
298 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
299 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
300 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
301 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
302 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
303 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
304 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
305 >;
306 };
307
308 pinctrl_usdhc3_gpio: usdhc3grpgpio {
309 fsl,pins = <
310 SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x00000021
311 SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
312 >;
313 };
314
315 pinctrl_usdhc3: usdhc3grp {
316 fsl,pins = <
317 SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
318 SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
319 SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
320 SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
321 SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
322 SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
323 SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
324 >;
325 };
326
327 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
328 fsl,pins = <
329 SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
330 SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
331 SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
332 SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
333 SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
334 SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
335 SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
336 >;
337 };
338
339 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
340 fsl,pins = <
341 SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
342 SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
343 SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
344 SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
345 SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
346 SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
347 SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
348 >;
349 };
350 };
351};
352
353&lpuart0 { /* console */
354 pinctrl-names = "default";
355 pinctrl-0 = <&pinctrl_lpuart0>;
356 status = "okay";
357};
358
359&lpuart1 { /* Q7 connector */
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_lpuart1>;
362 status = "okay";
363};
364
365&pd_dma_lpuart0 {
366 debug_console;
367};
368
369&usdhc1 {
370 pinctrl-names = "default", "state_100mhz", "state_200mhz";
371 pinctrl-0 = <&pinctrl_usdhc1>;
372 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
373 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
374 bus-width = <8>;
375 non-removable;
376 status = "okay";
377};
378
379&usdhc2 {
380 pinctrl-names = "default", "state_100mhz", "state_200mhz";
381 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
382 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
383 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
384 bus-width = <4>;
385 cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
386 wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
387 vmmc-supply = <&reg_usdhc2_vmmc>;
388 fsl,tuning-start-tap = <20>;
389 fsl,tuning-step= <2>;
390 status = "okay";
391};
392
393&usdhc3 {
394 pinctrl-names = "default", "state_100mhz", "state_200mhz";
395 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
396 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
397 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
398 bus-width = <4>;
399 cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
400 vmmc-supply = <&reg_usdhc3_vmmc>;
401 fsl,tuning-start-tap = <20>;
402 fsl,tuning-step= <2>;
403 status = "okay";
404};