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git01.mediatek.com / filogic / uboot / d5aa5058a0191c631027186ad9dda0322cefe5d8 / . / arch / arm / dts / imx8mn-var-som.dtsi
blob: 87b5e23c766f7361cdb6b613603e2d80c23c60b8 [file] [log] [blame]
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 * Copyright 2019-2020 Variscite Ltd.
5 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
6 */
7
8#include "imx8mn.dtsi"
9
10/ {
11 model = "Variscite VAR-SOM-MX8MN module";
12 compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
13
14 chosen {
15 stdout-path = &uart4;
16 };
17
18 memory@40000000 {
19 device_type = "memory";
20 reg = <0x0 0x40000000 0 0x40000000>;
21 };
22
23 reg_eth_phy: regulator-eth-phy {
24 compatible = "regulator-fixed";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_reg_eth_phy>;
27 regulator-name = "eth_phy_pwr";
28 regulator-min-microvolt = <3300000>;
29 regulator-max-microvolt = <3300000>;
30 gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
31 enable-active-high;
32 };
33};
34
35&A53_0 {
36 cpu-supply = <&buck2_reg>;
37};
38
39&A53_1 {
40 cpu-supply = <&buck2_reg>;
41};
42
43&A53_2 {
44 cpu-supply = <&buck2_reg>;
45};
46
47&A53_3 {
48 cpu-supply = <&buck2_reg>;
49};
50
51&ecspi1 {
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_ecspi1>;
54 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
55 <&gpio1 0 GPIO_ACTIVE_LOW>;
56 /delete-property/ dmas;
57 /delete-property/ dma-names;
58 status = "okay";
59
60 /* Resistive touch controller */
61 touchscreen@0 {
62 reg = <0>;
63 compatible = "ti,ads7846";
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_restouch>;
66 interrupt-parent = <&gpio1>;
67 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
68
69 spi-max-frequency = <1500000>;
70 pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
71
72 ti,x-min = /bits/ 16 <125>;
Marcel Ziswilera1033b82022-07-21 15:43:37 +0200[diff] [blame]73 touchscreen-size-x = <4008>;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]74 ti,y-min = /bits/ 16 <282>;
Marcel Ziswilera1033b82022-07-21 15:43:37 +0200[diff] [blame]75 touchscreen-size-y = <3864>;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]76 ti,x-plate-ohms = /bits/ 16 <180>;
Marcel Ziswilera1033b82022-07-21 15:43:37 +0200[diff] [blame]77 touchscreen-max-pressure = <255>;
78 touchscreen-average-samples = <10>;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]79 ti,debounce-tol = /bits/ 16 <3>;
80 ti,debounce-rep = /bits/ 16 <1>;
81 ti,settle-delay-usec = /bits/ 16 <150>;
82 ti,keep-vref-on;
83 wakeup-source;
84 };
85};
86
87&fec1 {
88 pinctrl-names = "default", "sleep";
89 pinctrl-0 = <&pinctrl_fec1>;
90 pinctrl-1 = <&pinctrl_fec1_sleep>;
91 phy-mode = "rgmii";
92 phy-handle = <&ethphy>;
93 phy-supply = <&reg_eth_phy>;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]94 fsl,magic-packet;
95 status = "okay";
96
97 mdio {
98 #address-cells = <1>;
99 #size-cells = <0>;
100
101 ethphy: ethernet-phy@4 {
102 compatible = "ethernet-phy-ieee802.3-c22";
103 reg = <4>;
Marcel Ziswilera1033b82022-07-21 15:43:37 +0200[diff] [blame]104 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
105 reset-assert-us = <10000>;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]106 };
107 };
108};
109
110&i2c1 {
111 clock-frequency = <400000>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_i2c1>;
114 status = "okay";
115
116 pmic@4b {
117 compatible = "rohm,bd71847";
118 reg = <0x4b>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_pmic>;
121 interrupt-parent = <&gpio2>;
122 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
123 rohm,reset-snvs-powered;
124
125 regulators {
126 buck1_reg: BUCK1 {
127 regulator-name = "buck1";
128 regulator-min-microvolt = <700000>;
129 regulator-max-microvolt = <1300000>;
130 regulator-boot-on;
131 regulator-always-on;
132 regulator-ramp-delay = <1250>;
133 };
134
135 buck2_reg: BUCK2 {
136 regulator-name = "buck2";
137 regulator-min-microvolt = <700000>;
138 regulator-max-microvolt = <1300000>;
139 regulator-boot-on;
140 regulator-always-on;
141 regulator-ramp-delay = <1250>;
142 rohm,dvs-run-voltage = <1000000>;
143 rohm,dvs-idle-voltage = <900000>;
144 };
145
146 buck3_reg: BUCK3 {
147 regulator-name = "buck3";
148 regulator-min-microvolt = <700000>;
149 regulator-max-microvolt = <1350000>;
150 regulator-boot-on;
151 regulator-always-on;
152 };
153
154 buck4_reg: BUCK4 {
155 regulator-name = "buck4";
156 regulator-min-microvolt = <2600000>;
157 regulator-max-microvolt = <3300000>;
158 regulator-boot-on;
159 regulator-always-on;
160 };
161
162 buck5_reg: BUCK5 {
163 regulator-name = "buck5";
164 regulator-min-microvolt = <1605000>;
165 regulator-max-microvolt = <1995000>;
166 regulator-boot-on;
167 regulator-always-on;
168 };
169
170 buck6_reg: BUCK6 {
171 regulator-name = "buck6";
172 regulator-min-microvolt = <800000>;
173 regulator-max-microvolt = <1400000>;
174 regulator-boot-on;
175 regulator-always-on;
176 };
177
178 ldo1_reg: LDO1 {
179 regulator-name = "ldo1";
180 regulator-min-microvolt = <1600000>;
181 regulator-max-microvolt = <1900000>;
182 regulator-boot-on;
183 regulator-always-on;
184 };
185
186 ldo2_reg: LDO2 {
187 regulator-name = "ldo2";
188 regulator-min-microvolt = <800000>;
189 regulator-max-microvolt = <900000>;
190 regulator-boot-on;
191 regulator-always-on;
192 };
193
194 ldo3_reg: LDO3 {
195 regulator-name = "ldo3";
196 regulator-min-microvolt = <1800000>;
197 regulator-max-microvolt = <3300000>;
198 regulator-boot-on;
199 regulator-always-on;
200 };
201
202 ldo4_reg: LDO4 {
203 regulator-name = "ldo4";
204 regulator-min-microvolt = <900000>;
205 regulator-max-microvolt = <1800000>;
206 regulator-always-on;
207 };
208
209 ldo5_reg: LDO5 {
210 regulator-compatible = "ldo5";
211 regulator-min-microvolt = <1800000>;
212 regulator-max-microvolt = <1800000>;
213 regulator-always-on;
214 };
215
216 ldo6_reg: LDO6 {
217 regulator-name = "ldo6";
218 regulator-min-microvolt = <900000>;
219 regulator-max-microvolt = <1800000>;
220 regulator-boot-on;
221 regulator-always-on;
222 };
223 };
224 };
225};
226
227&i2c3 {
228 clock-frequency = <400000>;
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_i2c3>;
231 status = "okay";
232
233 /* TODO: configure audio, as of now just put a placeholder */
234 wm8904: codec@1a {
235 compatible = "wlf,wm8904";
236 reg = <0x1a>;
237 status = "disabled";
238 };
239};
240
241&snvs_pwrkey {
242 status = "okay";
243};
244
245/* Bluetooth */
246&uart2 {
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_uart2>;
249 assigned-clocks = <&clk IMX8MN_CLK_UART2>;
250 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
251 uart-has-rtscts;
252 status = "okay";
253};
254
255/* Console */
256&uart4 {
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_uart4>;
259 status = "okay";
260};
261
262&usbotg1 {
Marcel Ziswilera1033b82022-07-21 15:43:37 +0200[diff] [blame]263 dr_mode = "otg";
264 usb-role-switch;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]265 status = "okay";
266};
267
268/* WIFI */
269&usdhc1 {
270 #address-cells = <1>;
271 #size-cells = <0>;
272 pinctrl-names = "default", "state_100mhz", "state_200mhz";
273 pinctrl-0 = <&pinctrl_usdhc1>;
274 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
275 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
276 bus-width = <4>;
277 non-removable;
278 keep-power-in-suspend;
279 status = "okay";
280
281 brcmf: bcrmf@1 {
282 reg = <1>;
283 compatible = "brcm,bcm4329-fmac";
284 };
285};
286
287/* SD */
288&usdhc2 {
289 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
290 assigned-clock-rates = <200000000>;
291 pinctrl-names = "default", "state_100mhz", "state_200mhz";
292 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
293 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
294 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
295 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
296 bus-width = <4>;
297 vmmc-supply = <&reg_usdhc2_vmmc>;
298 status = "okay";
299};
300
301/* eMMC */
302&usdhc3 {
303 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
304 assigned-clock-rates = <400000000>;
305 pinctrl-names = "default", "state_100mhz", "state_200mhz";
306 pinctrl-0 = <&pinctrl_usdhc3>;
307 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
308 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
309 bus-width = <8>;
310 non-removable;
311 status = "okay";
312};
313
314&wdog1 {
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_wdog>;
317 fsl,ext-reset-output;
318 status = "okay";
319};
320
321&iomuxc {
322 pinctrl_ecspi1: ecspi1grp {
323 fsl,pins = <
324 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
325 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
326 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
327 MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13
328 MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13
329 >;
330 };
331
332 pinctrl_fec1: fec1grp {
333 fsl,pins = <
334 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
335 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
336 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
337 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
338 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
339 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
340 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
341 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
342 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
343 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
344 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
345 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
346 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
347 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
348 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
349 >;
350 };
351
352 pinctrl_fec1_sleep: fec1sleepgrp {
353 fsl,pins = <
354 MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
355 MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
356 MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
357 MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
358 MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
359 MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
360 MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
361 MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
362 MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
363 MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
364 MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
365 MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
366 MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
367 MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
368 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120
369 >;
370 };
371
372 pinctrl_i2c1: i2c1grp {
373 fsl,pins = <
374 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
375 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
376 >;
377 };
378
379 pinctrl_i2c3: i2c3grp {
380 fsl,pins = <
381 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
382 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
383 >;
384 };
385
386 pinctrl_pmic: pmicirqgrp {
387 fsl,pins = <
388 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
389 >;
390 };
391
392 pinctrl_reg_eth_phy: regethphygrp {
393 fsl,pins = <
394 MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
395 >;
396 };
397
398 pinctrl_restouch: restouchgrp {
399 fsl,pins = <
400 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
401 >;
402 };
403
404 pinctrl_uart2: uart2grp {
405 fsl,pins = <
406 MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
407 MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
408 MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
409 MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
410 >;
411 };
412
413 pinctrl_uart4: uart4grp {
414 fsl,pins = <
415 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
416 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
417 >;
418 };
419
420 pinctrl_usdhc1: usdhc1grp {
421 fsl,pins = <
422 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
423 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
424 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
425 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
426 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
427 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
428 >;
429 };
430
431 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
432 fsl,pins = <
433 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
434 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
435 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
436 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
437 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
438 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
439 >;
440 };
441
442 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
443 fsl,pins = <
444 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
445 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
446 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
447 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
448 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
449 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
450 >;
451 };
452
453 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
454 fsl,pins = <
455 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
456 >;
457 };
458
459 pinctrl_usdhc2: usdhc2grp {
460 fsl,pins = <
461 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
462 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
463 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
464 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
465 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
466 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
467 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
468 >;
469 };
470
471 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
472 fsl,pins = <
473 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
474 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
475 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
476 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
477 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
478 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
479 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
480 >;
481 };
482
483 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
484 fsl,pins = <
485 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
486 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
487 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
488 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
489 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
490 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
491 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
492 >;
493 };
494
495 pinctrl_usdhc3: usdhc3grp {
496 fsl,pins = <
497 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
498 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
499 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
500 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
501 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
502 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
503 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
504 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
505 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
506 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
507 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
508 >;
509 };
510
511 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
512 fsl,pins = <
513 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
514 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
515 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
516 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
517 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
518 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
519 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
520 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
521 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
522 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
523 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
524 >;
525 };
526
527 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
528 fsl,pins = <
529 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
530 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
531 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
532 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
533 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
534 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
535 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
536 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
537 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
538 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
539 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
540 >;
541 };
542
543 pinctrl_wdog: wdoggrp {
544 fsl,pins = <
545 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
546 >;
547 };
548};