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git01.mediatek.com / filogic / uboot / d5aa5058a0191c631027186ad9dda0322cefe5d8 / . / arch / arm / dts / imx6qdl-tqma6a.dtsi
blob: 7dc3f0005b0f0e5c213895e3ec0f31ddd3554e2b [file] [log] [blame]
Marcel Ziswiler5d4bcee2022-07-21 15:27:26 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Sascha Hauer, Pengutronix
4 * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8
9&fec {
10 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
11 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
12 fsl,err006687-workaround-present;
13};
Michael Krummsdorf67510d02020-04-09 15:21:37 +0200[diff] [blame]14
15&i2c1 {
Marcel Ziswiler5d4bcee2022-07-21 15:27:26 +0200[diff] [blame]16 pinctrl-names = "default", "gpio";
17 pinctrl-0 = <&pinctrl_i2c1>;
18 pinctrl-1 = <&pinctrl_i2c1_recovery>;
19 scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
20 sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
Michael Krummsdorf67510d02020-04-09 15:21:37 +0200[diff] [blame]21 clock-frequency = <100000>;
22 status = "okay";
23
Marcel Ziswiler5d4bcee2022-07-21 15:27:26 +0200[diff] [blame]24 pmic: pmic@8 {
Michael Krummsdorf67510d02020-04-09 15:21:37 +0200[diff] [blame]25 compatible = "fsl,pfuze100";
26 reg = <0x08>;
27 };
28
Marcel Ziswiler5d4bcee2022-07-21 15:27:26 +0200[diff] [blame]29 sensor@48 {
30 compatible = "national,lm75";
Michael Krummsdorf67510d02020-04-09 15:21:37 +0200[diff] [blame]31 reg = <0x48>;
32 };
33
Marcel Ziswiler5d4bcee2022-07-21 15:27:26 +0200[diff] [blame]34 eeprom@50 {
35 compatible = "st,24c64", "atmel,24c64";
Michael Krummsdorf67510d02020-04-09 15:21:37 +0200[diff] [blame]36 reg = <0x50>;
37 pagesize = <32>;
38 };
39};
40
Marcel Ziswiler5d4bcee2022-07-21 15:27:26 +0200[diff] [blame]41&iomuxc {
42 /*
43 * This pinmuxing is required for the ERR006687 workaround. Board
44 * DTS files that enable the FEC controller with
45 * fsl,err006687-workaround-present must include this group.
46 */
47 pinctrl_enet_fix: enetfixgrp {
48 fsl,pins = <
49 /* ENET ping patch */
50 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
51 >;
52 };
53};