John Rigby | 25a3362 | 2011-04-19 10:42:42 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) ST-Ericsson SA 2009 |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 17 | */ |
| 18 | |
| 19 | #include <config.h> |
| 20 | #include <common.h> |
| 21 | #include <i2c.h> |
| 22 | #include <asm/types.h> |
| 23 | #include <asm/io.h> |
| 24 | #include <asm/errno.h> |
| 25 | #include <asm/arch/clock.h> |
| 26 | #include <asm/arch/gpio.h> |
| 27 | #include <asm/arch/hardware.h> |
| 28 | #include <asm/arch/sys_proto.h> |
| 29 | #ifdef CONFIG_MMC |
Dirk Behme | 75d3342 | 2011-07-09 20:52:17 +0000 | [diff] [blame] | 30 | #include "prcmu-fw.h" |
John Rigby | 25a3362 | 2011-04-19 10:42:42 +0000 | [diff] [blame] | 31 | #include "../../../drivers/mmc/arm_pl180_mmci.h" |
| 32 | #endif |
| 33 | |
| 34 | #define NOMADIK_PER4_BASE (0x80150000) |
| 35 | #define NOMADIK_BACKUPRAM0_BASE (NOMADIK_PER4_BASE + 0x00000) |
| 36 | #define NOMADIK_BACKUPRAM1_BASE (NOMADIK_PER4_BASE + 0x01000) |
| 37 | |
| 38 | /* Power, Reset, Clock Management Unit */ |
| 39 | /* |
| 40 | * SVA: Smart Video Accelerator |
| 41 | * SIA: Smart Imaging Accelerator |
| 42 | * SGA: Smart Graphic accelerator |
| 43 | * B2R2: Graphic blitter |
| 44 | */ |
| 45 | #define PRCMU_BASE CFG_PRCMU_BASE /* 0x80157000 for U8500 */ |
| 46 | #define PRCM_ARMCLKFIX_MGT_REG (PRCMU_BASE + 0x000) |
| 47 | #define PRCM_ACLK_MGT_REG (PRCMU_BASE + 0x004) |
| 48 | #define PRCM_SVAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x008) |
| 49 | #define PRCM_SIAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x00C) |
| 50 | #define PRCM_SAAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x010) |
| 51 | #define PRCM_SGACLK_MGT_REG (PRCMU_BASE + 0x014) |
| 52 | #define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018) |
| 53 | #define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C) |
| 54 | #define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020) |
| 55 | #define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024) |
| 56 | #define PRCM_SLIMCLK_MGT_REG (PRCMU_BASE + 0x028) |
| 57 | #define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C) |
| 58 | #define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030) |
| 59 | #define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034) |
| 60 | #define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038) |
| 61 | #define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C) |
| 62 | #define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040) |
| 63 | #define PRCM_DMACLK_MGT_REG (PRCMU_BASE + 0x074) |
| 64 | #define PRCM_B2R2CLK_MGT_REG (PRCMU_BASE + 0x078) |
| 65 | |
| 66 | #define PRCM_PLLSOC0_FREQ_REG (PRCMU_BASE + 0x080) |
| 67 | #define PRCM_PLLSOC1_FREQ_REG (PRCMU_BASE + 0x084) |
| 68 | #define PRCM_PLLARM_FREQ_REG (PRCMU_BASE + 0x088) |
| 69 | #define PRCM_PLLDDR_FREQ_REG (PRCMU_BASE + 0x08C) |
| 70 | #define PRCM_ARM_CHGCLKREQ_REG (PRCMU_BASE + 0x114) |
| 71 | |
| 72 | #define PRCM_TCR (PRCMU_BASE + 0x1C8) |
| 73 | |
| 74 | /* |
| 75 | * Memory controller register |
| 76 | */ |
| 77 | #define DMC_BASE_ADDR 0x80156000 |
| 78 | #define DMC_CTL_97 (DMC_BASE_ADDR + 0x184) |
| 79 | |
| 80 | int board_id; /* set in board_late_init() */ |
| 81 | |
| 82 | /* PLLs for clock management registers */ |
| 83 | enum { |
| 84 | GATED = 0, |
| 85 | PLLSOC0, /* pllsw = 001, ffs() = 1 */ |
| 86 | PLLSOC1, /* pllsw = 010, ffs() = 2 */ |
| 87 | PLLDDR, /* pllsw = 100, ffs() = 3 */ |
| 88 | PLLARM, |
| 89 | }; |
| 90 | |
| 91 | static struct pll_freq_regs { |
| 92 | int idx; /* index fror pll_name and pll_khz arrays */ |
| 93 | uint32_t addr; |
| 94 | } pll_freq_regs[] = { |
| 95 | {PLLSOC0, PRCM_PLLSOC0_FREQ_REG}, |
| 96 | {PLLSOC1, PRCM_PLLSOC1_FREQ_REG}, |
| 97 | {PLLDDR, PRCM_PLLDDR_FREQ_REG}, |
| 98 | {PLLARM, PRCM_PLLARM_FREQ_REG}, |
| 99 | {0, 0}, |
| 100 | }; |
| 101 | |
| 102 | static const char *pll_name[5] = {"GATED", "SOC0", "SOC1", "DDR", "ARM"}; |
| 103 | static uint32_t pll_khz[5]; /* use ffs(pllsw(reg)) as index for 0..3 */ |
| 104 | |
| 105 | static struct clk_mgt_regs { |
| 106 | uint32_t addr; |
| 107 | uint32_t val; |
| 108 | const char *descr; |
| 109 | } clk_mgt_regs[] = { |
| 110 | /* register content taken from bootrom settings */ |
| 111 | {PRCM_ARMCLKFIX_MGT_REG, 0x0120, "ARMCLKFIX"}, /* ena, SOC0/0, ??? */ |
| 112 | {PRCM_ACLK_MGT_REG, 0x0125, "ACLK"}, /* ena, SOC0/5, 160 MHz */ |
| 113 | {PRCM_SVAMMDSPCLK_MGT_REG, 0x1122, "SVA"}, /* ena, SOC0/2, 400 MHz */ |
| 114 | {PRCM_SIAMMDSPCLK_MGT_REG, 0x0022, "SIA"}, /* dis, SOC0/2, 400 MHz */ |
| 115 | {PRCM_SAAMMDSPCLK_MGT_REG, 0x0822, "SAA"}, /* dis, SOC0/4, 200 MHz */ |
| 116 | {PRCM_SGACLK_MGT_REG, 0x0024, "SGA"}, /* dis, SOC0/4, 200 MHz */ |
| 117 | {PRCM_UARTCLK_MGT_REG, 0x0300, "UART"}, /* ena, GATED, CLK38 */ |
| 118 | {PRCM_MSPCLK_MGT_REG, 0x0200, "MSP"}, /* dis, GATED, CLK38 */ |
| 119 | {PRCM_I2CCLK_MGT_REG, 0x0130, "I2C"}, /* ena, SOC0/16, 50 MHz */ |
| 120 | {PRCM_SDMMCCLK_MGT_REG, 0x0130, "SDMMC"}, /* ena, SOC0/16, 50 MHz */ |
| 121 | {PRCM_PER1CLK_MGT_REG, 0x126, "PER1"}, /* ena, SOC0/6, 133 MHz */ |
| 122 | {PRCM_PER2CLK_MGT_REG, 0x126, "PER2"}, /* ena, SOC0/6, 133 MHz */ |
| 123 | {PRCM_PER3CLK_MGT_REG, 0x126, "PER3"}, /* ena, SOC0/6, 133 MHz */ |
| 124 | {PRCM_PER5CLK_MGT_REG, 0x126, "PER5"}, /* ena, SOC0/6, 133 MHz */ |
| 125 | {PRCM_PER6CLK_MGT_REG, 0x126, "PER6"}, /* ena, SOC0/6, 133 MHz */ |
| 126 | {PRCM_PER7CLK_MGT_REG, 0x128, "PER7"}, /* ena, SOC0/8, 100 MHz */ |
| 127 | {PRCM_DMACLK_MGT_REG, 0x125, "DMA"}, /* ena, SOC0/5, 160 MHz */ |
| 128 | {PRCM_B2R2CLK_MGT_REG, 0x025, "B2R2"}, /* dis, SOC0/5, 160 MHz */ |
| 129 | {0, 0, NULL}, |
| 130 | }; |
| 131 | |
| 132 | static void init_regs(void); |
| 133 | |
| 134 | DECLARE_GLOBAL_DATA_PTR; |
| 135 | #if defined(CONFIG_SHOW_BOOT_PROGRESS) |
| 136 | void show_boot_progress(int progress) |
| 137 | { |
| 138 | printf("Boot reached stage %d\n", progress); |
| 139 | } |
| 140 | #endif |
| 141 | |
| 142 | static unsigned int read_asicid(void) |
| 143 | { |
| 144 | unsigned int *address = (void *)U8500_BOOTROM_BASE |
| 145 | + U8500_BOOTROM_ASIC_ID_OFFSET; |
| 146 | return readl(address); |
| 147 | } |
| 148 | |
| 149 | int cpu_is_u8500v11(void) |
| 150 | { |
| 151 | return read_asicid() == 0x008500A1; |
| 152 | } |
| 153 | |
| 154 | /* |
| 155 | * Miscellaneous platform dependent initialisations |
| 156 | */ |
| 157 | |
| 158 | int board_early_init_f(void) |
| 159 | { |
| 160 | init_regs(); |
| 161 | return 0; |
| 162 | } |
| 163 | |
| 164 | int board_init(void) |
| 165 | { |
| 166 | uint32_t unused_cols_rows; |
| 167 | unsigned int nrows; |
| 168 | unsigned int ncols; |
| 169 | |
| 170 | gd->bd->bi_arch_number = 0x1A4; |
| 171 | gd->bd->bi_boot_params = 0x00000100; |
| 172 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; |
| 173 | |
| 174 | /* |
| 175 | * Assumption: 2 CS active, both CS have same layout. |
| 176 | * 15 rows max, 11 cols max (controller spec). |
| 177 | * memory chip has 8 banks, I/O width 32 bit. |
| 178 | * The correct way would be to read MR#8: I/O width and density, |
| 179 | * but this requires locking against the PRCMU firmware. |
| 180 | * Simplified approach: |
| 181 | * Read number of unused rows and columns from mem controller. |
| 182 | * size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes |
| 183 | */ |
| 184 | unused_cols_rows = readl(DMC_CTL_97); |
| 185 | nrows = 15 - (unused_cols_rows & 0x07); |
| 186 | ncols = 11 - ((unused_cols_rows & 0x0700) >> 8); |
| 187 | gd->bd->bi_dram[0].size = 2 * (1 << (nrows + ncols)) * 8 * 4; |
| 188 | |
| 189 | icache_enable(); |
| 190 | |
| 191 | return 0; |
| 192 | } |
| 193 | |
| 194 | int dram_init(void) |
| 195 | { |
| 196 | gd->ram_size = PHYS_SDRAM_SIZE_1; |
| 197 | |
| 198 | return 0; |
| 199 | } |
| 200 | |
| 201 | unsigned int addr_vall_arr[] = { |
| 202 | 0x8011F000, 0x0000FFFF, /* Clocks for HSI TODO: Enable reqd only */ |
| 203 | 0x8011F008, 0x00001CFF, /* Clocks for HSI TODO: Enable reqd only */ |
| 204 | 0x8000F000, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */ |
| 205 | 0x8000F008, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */ |
| 206 | 0x80157020, 0x00000150, /* I2C 48MHz clock */ |
| 207 | 0x8012F000, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */ |
| 208 | 0x8012F008, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */ |
| 209 | 0xA03DF000, 0x0000000D, /* Clock for MTU Timers */ |
| 210 | 0x8011E00C, 0x00000000, /* GPIO ALT FUNC for EMMC */ |
| 211 | 0x8011E004, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */ |
| 212 | 0x8011E020, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */ |
| 213 | 0x8011E024, 0x00000000, /* GPIO ALT FUNC for EMMC */ |
| 214 | 0x8012E000, 0x20000000, /* GPIO ALT FUNC for UART */ |
| 215 | 0x8012E00C, 0x00000000, /* GPIO ALT FUNC for SD */ |
| 216 | 0x8012E004, 0x0FFC0000, /* GPIO ALT FUNC for SD */ |
| 217 | 0x8012E020, 0x60000000, /* GPIO ALT FUNC for SD */ |
| 218 | 0x8012E024, 0x60000000, /* GPIO ALT FUNC for SD */ |
| 219 | 0x801571E4, 0x0000000C, /* PRCMU settings for B2R2, |
| 220 | PRCM_APE_RESETN_SET_REG */ |
| 221 | 0x80157024, 0x00000130, /* PRCMU settings for EMMC/SD */ |
| 222 | 0xA03FF000, 0x00000003, /* USB */ |
| 223 | 0xA03FF008, 0x00000001, /* USB */ |
| 224 | 0xA03FE00C, 0x00000000, /* USB */ |
| 225 | 0xA03FE020, 0x00000FFF, /* USB */ |
| 226 | 0xA03FE024, 0x00000000 /* USB */ |
| 227 | }; |
| 228 | |
Helmut Raiger | d5a184b | 2011-10-20 04:19:47 +0000 | [diff] [blame^] | 229 | #ifdef CONFIG_BOARD_LATE_INIT |
John Rigby | 25a3362 | 2011-04-19 10:42:42 +0000 | [diff] [blame] | 230 | #ifdef CONFIG_MMC |
| 231 | |
| 232 | #define LDO_VAUX3_MASK 0x3 |
| 233 | #define LDO_VAUX3_ENABLE 0x1 |
| 234 | #define VAUX3_VOLTAGE_2_9V 0xd |
| 235 | |
| 236 | #define AB8500_REGU_CTRL2 0x4 |
| 237 | #define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A |
| 238 | #define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421 |
| 239 | |
| 240 | static int hrefplus_mmc_power_init(void) |
| 241 | { |
| 242 | int ret; |
| 243 | int val; |
| 244 | |
| 245 | if (!cpu_is_u8500v11()) |
| 246 | return 0; |
| 247 | |
| 248 | /* |
| 249 | * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD |
| 250 | * card to work. This is done by enabling the regulators in the AB8500 |
| 251 | * via PRCMU I2C transactions. |
| 252 | * |
| 253 | * This code is derived from the handling of AB8500_LDO_VAUX3 in |
| 254 | * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux. |
| 255 | * |
| 256 | * Turn off and delay is required to have it work across soft reboots. |
| 257 | */ |
| 258 | |
| 259 | ret = prcmu_i2c_read(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG); |
| 260 | if (ret < 0) |
| 261 | goto out; |
| 262 | |
| 263 | val = ret; |
| 264 | |
| 265 | /* Turn off */ |
| 266 | ret = prcmu_i2c_write(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG, |
| 267 | val & ~LDO_VAUX3_MASK); |
| 268 | if (ret < 0) |
| 269 | goto out; |
| 270 | |
| 271 | udelay(10 * 1000); |
| 272 | |
| 273 | /* Set the voltage to 2.9V */ |
| 274 | ret = prcmu_i2c_write(AB8500_REGU_CTRL2, |
| 275 | AB8500_REGU_VRF1VAUX3_SEL_REG, |
| 276 | VAUX3_VOLTAGE_2_9V); |
| 277 | if (ret < 0) |
| 278 | goto out; |
| 279 | |
| 280 | val = val & ~LDO_VAUX3_MASK; |
| 281 | val = val | LDO_VAUX3_ENABLE; |
| 282 | |
| 283 | /* Turn on the supply */ |
| 284 | ret = prcmu_i2c_write(AB8500_REGU_CTRL2, |
| 285 | AB8500_REGU_VRF1VAUX3_REGU_REG, val); |
| 286 | |
| 287 | out: |
| 288 | return ret; |
| 289 | } |
| 290 | #endif |
| 291 | /* |
| 292 | * called after all initialisation were done, but before the generic |
| 293 | * mmc_initialize(). |
| 294 | */ |
| 295 | int board_late_init(void) |
| 296 | { |
| 297 | uchar byte; |
| 298 | |
| 299 | /* |
| 300 | * Determine and set board_id environment variable |
| 301 | * 0: mop500, 1: href500 |
| 302 | * Above boards have different GPIO expander chips which we can |
| 303 | * distinguish by the chip id. |
| 304 | * |
| 305 | * The board_id environment variable is needed for the Linux bootargs. |
| 306 | */ |
| 307 | (void) i2c_set_bus_num(0); |
| 308 | (void) i2c_read(CONFIG_SYS_I2C_GPIOE_ADDR, 0x80, 1, &byte, 1); |
| 309 | if (byte == 0x01) { |
| 310 | board_id = 0; |
| 311 | setenv("board_id", "0"); |
| 312 | } else { |
| 313 | board_id = 1; |
| 314 | setenv("board_id", "1"); |
| 315 | } |
| 316 | #ifdef CONFIG_MMC |
| 317 | hrefplus_mmc_power_init(); |
| 318 | |
| 319 | /* |
| 320 | * config extended GPIO pins for level shifter and |
| 321 | * SDMMC_ENABLE |
| 322 | */ |
| 323 | if (board_id == 0) { |
| 324 | /* MOP500 */ |
| 325 | byte = 0x0c; |
| 326 | (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x89, 1, &byte, 1); |
| 327 | (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x83, 1, &byte, 1); |
| 328 | } else { |
| 329 | /* HREF */ |
| 330 | /* set the direction of GPIO KPY9 and KPY10 */ |
| 331 | byte = 0x06; |
| 332 | (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC8, 1, &byte, 1); |
| 333 | /* must be a multibyte access */ |
| 334 | (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC4, 1, |
| 335 | (uchar []) {0x06, 0x06}, 2); |
| 336 | } |
| 337 | #endif /* CONFIG_MMC */ |
| 338 | /* |
| 339 | * Create a memargs variable which points uses either the memargs256 or |
| 340 | * memargs512 environment variable, depending on the memory size. |
| 341 | * memargs is used to build the bootargs, memargs256 and memargs512 are |
| 342 | * stored in the environment. |
| 343 | */ |
| 344 | if (gd->bd->bi_dram[0].size == 0x10000000) { |
| 345 | setenv("memargs", "setenv bootargs ${bootargs} ${memargs256}"); |
| 346 | setenv("mem", "256M"); |
| 347 | } else { |
| 348 | setenv("memargs", "setenv bootargs ${bootargs} ${memargs512}"); |
| 349 | setenv("mem", "512M"); |
| 350 | } |
| 351 | |
| 352 | return 0; |
| 353 | } |
Helmut Raiger | d5a184b | 2011-10-20 04:19:47 +0000 | [diff] [blame^] | 354 | #endif /* CONFIG_BOARD_LATE_INIT */ |
John Rigby | 25a3362 | 2011-04-19 10:42:42 +0000 | [diff] [blame] | 355 | |
| 356 | static void early_gpio_setup(struct gpio_register *gpio_reg, u32 bits) |
| 357 | { |
| 358 | writel(readl(&gpio_reg->gpio_dats) | bits, &gpio_reg->gpio_dats); |
| 359 | writel(readl(&gpio_reg->gpio_pdis) & ~bits, &gpio_reg->gpio_pdis); |
| 360 | } |
| 361 | |
| 362 | static void init_regs(void) |
| 363 | { |
| 364 | /* FIXME Remove magic register array settings for ED also */ |
| 365 | struct prcmu *prcmu = (struct prcmu *) U8500_PRCMU_BASE; |
| 366 | |
| 367 | /* Enable timers */ |
| 368 | writel(1 << 17, &prcmu->tcr); |
| 369 | |
| 370 | u8500_prcmu_enable(&prcmu->per1clk_mgt); |
| 371 | u8500_prcmu_enable(&prcmu->per2clk_mgt); |
| 372 | u8500_prcmu_enable(&prcmu->per3clk_mgt); |
| 373 | u8500_prcmu_enable(&prcmu->per5clk_mgt); |
| 374 | u8500_prcmu_enable(&prcmu->per6clk_mgt); |
| 375 | u8500_prcmu_enable(&prcmu->per7clk_mgt); |
| 376 | |
| 377 | u8500_prcmu_enable(&prcmu->uartclk_mgt); |
| 378 | u8500_prcmu_enable(&prcmu->i2cclk_mgt); |
| 379 | |
| 380 | u8500_prcmu_enable(&prcmu->sdmmcclk_mgt); |
| 381 | |
| 382 | u8500_clock_enable(1, 9, -1); /* GPIO0 */ |
| 383 | |
| 384 | u8500_clock_enable(2, 11, -1); /* GPIO1 */ |
| 385 | |
| 386 | u8500_clock_enable(3, 8, -1); /* GPIO2 */ |
| 387 | u8500_clock_enable(5, 1, -1); /* GPIO3 */ |
| 388 | |
| 389 | u8500_clock_enable(3, 6, 6); /* UART2 */ |
| 390 | |
| 391 | gpio_altfuncenable(GPIO_ALT_I2C_0, "I2C0"); |
| 392 | u8500_clock_enable(3, 3, 3); /* I2C0 */ |
| 393 | |
| 394 | early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x60000000); |
| 395 | gpio_altfuncenable(GPIO_ALT_UART_2, "UART2"); |
| 396 | |
| 397 | early_gpio_setup((struct gpio_register *)U8500_GPIO_6_BASE, 0x0000ffe0); |
| 398 | gpio_altfuncenable(GPIO_ALT_EMMC, "EMMC"); |
| 399 | |
| 400 | early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x0000ffe0); |
| 401 | gpio_altfuncenable(GPIO_ALT_SD_CARD0, "SDCARD"); |
| 402 | |
| 403 | u8500_clock_enable(1, 5, 5); /* SDI0 */ |
| 404 | u8500_clock_enable(2, 4, 2); /* SDI4 */ |
| 405 | |
| 406 | u8500_clock_enable(6, 7, -1); /* MTU0 */ |
| 407 | u8500_clock_enable(3, 4, 4); /* SDI2 */ |
| 408 | |
| 409 | early_gpio_setup((struct gpio_register *)U8500_GPIO_4_BASE, 0x000007ff); |
| 410 | gpio_altfuncenable(GPIO_ALT_POP_EMMC, "EMMC"); |
| 411 | |
| 412 | /* |
| 413 | * Enabling clocks for all devices which are AMBA devices in the |
| 414 | * kernel. Otherwise they will not get probe()'d because the |
| 415 | * peripheral ID register will not be powered. |
| 416 | */ |
| 417 | |
| 418 | /* XXX: some of these differ between ED/V1 */ |
| 419 | |
| 420 | u8500_clock_enable(1, 1, 1); /* UART1 */ |
| 421 | u8500_clock_enable(1, 0, 0); /* UART0 */ |
| 422 | |
| 423 | u8500_clock_enable(3, 2, 2); /* SSP1 */ |
| 424 | u8500_clock_enable(3, 1, 1); /* SSP0 */ |
| 425 | |
| 426 | u8500_clock_enable(2, 8, -1); /* SPI0 */ |
| 427 | u8500_clock_enable(2, 5, 3); /* MSP2 */ |
| 428 | } |
| 429 | |
| 430 | #ifdef CONFIG_MMC |
| 431 | static int u8500_mmci_board_init(void) |
| 432 | { |
| 433 | enum gpio_error error; |
| 434 | struct gpio_register *gpio_base_address; |
| 435 | |
| 436 | gpio_base_address = (void *)(U8500_GPIO_0_BASE); |
| 437 | gpio_base_address->gpio_dats |= 0xFFC0000; |
| 438 | gpio_base_address->gpio_pdis &= ~0xFFC0000; |
| 439 | |
| 440 | /* save the GPIO0 AFSELA register */ |
| 441 | error = gpio_altfuncenable(GPIO_ALT_SD_CARD0, "MMC"); |
| 442 | if (error != GPIO_OK) { |
| 443 | printf("u8500_mmci_board_init() gpio_altfuncenable failed\n"); |
| 444 | return -ENODEV; |
| 445 | } |
| 446 | return 0; |
| 447 | } |
| 448 | |
| 449 | int board_mmc_init(bd_t *bd) |
| 450 | { |
| 451 | if (u8500_mmci_board_init()) |
| 452 | return -ENODEV; |
| 453 | |
| 454 | if (arm_pl180_mmci_init()) |
| 455 | return -ENODEV; |
| 456 | return 0; |
| 457 | } |
| 458 | #endif |
| 459 | |
| 460 | |
| 461 | /* |
| 462 | * get_pll_freq_khz - return PLL frequency in kHz |
| 463 | */ |
| 464 | static uint32_t get_pll_freq_khz(uint32_t inclk_khz, uint32_t freq_reg) |
| 465 | { |
| 466 | uint32_t idf, ldf, odf, seldiv, phi; |
| 467 | |
| 468 | /* |
| 469 | * PLLOUTCLK = PHI = (INCLK*LDF)/(2*ODF*IDF) if SELDIV2=0 |
| 470 | * PLLOUTCLK = PHI = (INCLK*LDF)/(4*ODF*IDF) if SELDIV2=1 |
| 471 | * where: |
| 472 | * IDF=R(2:0) (when R=000, IDF=1d) |
| 473 | * LDF = 2*D(7:0) (D must be greater than or equal to 6) |
| 474 | * ODF = N(5:0) (when N=000000, 0DF=1d) |
| 475 | */ |
| 476 | |
| 477 | idf = (freq_reg & 0x70000) >> 16; |
| 478 | ldf = (freq_reg & 0xff) * 2; |
| 479 | odf = (freq_reg & 0x3f00) >> 8; |
| 480 | seldiv = (freq_reg & 0x01000000) >> 24; |
| 481 | phi = (inclk_khz * ldf) / (2 * odf * idf); |
| 482 | if (seldiv) |
| 483 | phi = phi/2; |
| 484 | |
| 485 | return phi; |
| 486 | } |
| 487 | |
| 488 | int do_clkinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
| 489 | { |
| 490 | uint32_t inclk_khz; |
| 491 | uint32_t reg, phi; |
| 492 | uint32_t clk_khz; |
| 493 | unsigned int clk_sel; |
| 494 | struct clk_mgt_regs *clks = clk_mgt_regs; |
| 495 | struct pll_freq_regs *plls = pll_freq_regs; |
| 496 | |
| 497 | /* |
| 498 | * Go through list of PLLs. |
| 499 | * Initialise pll out frequency array (pll_khz) and print frequency. |
| 500 | */ |
| 501 | inclk_khz = 38400; /* 38.4 MHz */ |
| 502 | while (plls->addr) { |
| 503 | reg = readl(plls->addr); |
| 504 | phi = get_pll_freq_khz(inclk_khz, reg); |
| 505 | pll_khz[plls->idx] = phi; |
| 506 | printf("%s PLL out frequency: %d.%d Mhz\n", |
| 507 | pll_name[plls->idx], phi/1000, phi % 1000); |
| 508 | plls++; |
| 509 | } |
| 510 | |
| 511 | /* check ARM clock source */ |
| 512 | reg = readl(PRCM_ARM_CHGCLKREQ_REG); |
| 513 | printf("A9 running on %s\n", |
| 514 | (reg & 1) ? "external clock" : "ARM PLL"); |
| 515 | |
| 516 | /* go through list of clk_mgt_reg */ |
| 517 | printf("\n%19s %9s %7s %9s enabled\n", |
| 518 | "name(addr)", "value", "PLL", "CLK[MHz]"); |
| 519 | while (clks->addr) { |
| 520 | reg = readl(clks->addr); |
| 521 | |
| 522 | /* convert bit position into array index */ |
| 523 | clk_sel = ffs((reg >> 5) & 0x7); /* PLLSW[2:0] */ |
| 524 | |
| 525 | if (reg & 0x200) |
| 526 | clk_khz = 38400; /* CLK38 is set */ |
| 527 | else if ((reg & 0x1f) == 0) |
| 528 | /* ARMCLKFIX_MGT is 0x120, e.g. div = 0 ! */ |
| 529 | clk_khz = 0; |
| 530 | else |
| 531 | clk_khz = pll_khz[clk_sel] / (reg & 0x1f); |
| 532 | |
| 533 | printf("%9s(%08x): %08x, %6s, %4d.%03d, %s\n", |
| 534 | clks->descr, clks->addr, reg, pll_name[clk_sel], |
| 535 | clk_khz / 1000, clk_khz % 1000, |
| 536 | (reg & 0x100) ? "ena" : "dis"); |
| 537 | clks++; |
| 538 | } |
| 539 | |
| 540 | return 0; |
| 541 | } |
| 542 | |
| 543 | U_BOOT_CMD( |
| 544 | clkinfo, 1, 1, do_clkinfo, |
| 545 | "print clock info", |
| 546 | "" |
| 547 | ); |