| Stelian Pop | 048bcfb | 2008-03-26 19:52:30 +0100 | [diff] [blame] | 1 | /* |
| Stelian Pop | d57846e | 2008-05-08 22:52:10 +0200 | [diff] [blame^] | 2 | * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9.h] |
| Stelian Pop | 048bcfb | 2008-03-26 19:52:30 +0100 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> |
| 5 | * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> |
| 6 | * Copyright (C) 2007 Atmel Corporation. |
| 7 | * |
| 8 | * Common definitions. |
| 9 | * Based on AT91CAP9 datasheet revision B (Preliminary). |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | */ |
| 16 | |
| 17 | #ifndef AT91CAP9_H |
| 18 | #define AT91CAP9_H |
| 19 | |
| 20 | /* |
| 21 | * Peripheral identifiers/interrupts. |
| 22 | */ |
| 23 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ |
| 24 | #define AT91_ID_SYS 1 /* System Peripherals */ |
| 25 | #define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */ |
| 26 | #define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */ |
| 27 | #define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */ |
| 28 | #define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */ |
| 29 | #define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */ |
| 30 | #define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */ |
| 31 | #define AT91CAP9_ID_US0 8 /* USART 0 */ |
| 32 | #define AT91CAP9_ID_US1 9 /* USART 1 */ |
| 33 | #define AT91CAP9_ID_US2 10 /* USART 2 */ |
| 34 | #define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */ |
| 35 | #define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */ |
| 36 | #define AT91CAP9_ID_CAN 13 /* CAN */ |
| 37 | #define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */ |
| 38 | #define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */ |
| 39 | #define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */ |
| 40 | #define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */ |
| 41 | #define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */ |
| 42 | #define AT91CAP9_ID_AC97C 19 /* AC97 Controller */ |
| 43 | #define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */ |
| 44 | #define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */ |
| 45 | #define AT91CAP9_ID_EMAC 22 /* Ethernet */ |
| 46 | #define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */ |
| 47 | #define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */ |
| 48 | #define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */ |
| 49 | #define AT91CAP9_ID_LCDC 26 /* LCD Controller */ |
| 50 | #define AT91CAP9_ID_DMA 27 /* DMA Controller */ |
| 51 | #define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */ |
| 52 | #define AT91CAP9_ID_UHP 29 /* USB Host Port */ |
| 53 | #define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ |
| 54 | #define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ |
| 55 | |
| 56 | /* |
| 57 | * User Peripheral physical base addresses. |
| 58 | */ |
| 59 | #define AT91CAP9_BASE_UDPHS 0xfff78000 |
| 60 | #define AT91CAP9_BASE_TCB0 0xfff7c000 |
| 61 | #define AT91CAP9_BASE_TC0 0xfff7c000 |
| 62 | #define AT91CAP9_BASE_TC1 0xfff7c040 |
| 63 | #define AT91CAP9_BASE_TC2 0xfff7c080 |
| 64 | #define AT91CAP9_BASE_MCI0 0xfff80000 |
| 65 | #define AT91CAP9_BASE_MCI1 0xfff84000 |
| 66 | #define AT91CAP9_BASE_TWI 0xfff88000 |
| 67 | #define AT91CAP9_BASE_US0 0xfff8c000 |
| 68 | #define AT91CAP9_BASE_US1 0xfff90000 |
| 69 | #define AT91CAP9_BASE_US2 0xfff94000 |
| 70 | #define AT91CAP9_BASE_SSC0 0xfff98000 |
| 71 | #define AT91CAP9_BASE_SSC1 0xfff9c000 |
| 72 | #define AT91CAP9_BASE_AC97C 0xfffa0000 |
| 73 | #define AT91CAP9_BASE_SPI0 0xfffa4000 |
| 74 | #define AT91CAP9_BASE_SPI1 0xfffa8000 |
| 75 | #define AT91CAP9_BASE_CAN 0xfffac000 |
| 76 | #define AT91CAP9_BASE_PWMC 0xfffb8000 |
| 77 | #define AT91CAP9_BASE_EMAC 0xfffbc000 |
| 78 | #define AT91CAP9_BASE_ADC 0xfffc0000 |
| 79 | #define AT91CAP9_BASE_ISI 0xfffc4000 |
| 80 | #define AT91_BASE_SYS 0xffffe200 |
| 81 | |
| 82 | /* |
| 83 | * System Peripherals (offset from AT91_BASE_SYS) |
| 84 | */ |
| 85 | #define AT91_ECC (0xffffe200 - AT91_BASE_SYS) |
| 86 | #define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) |
| 87 | #define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS) |
| 88 | #define AT91_SMC (0xffffe800 - AT91_BASE_SYS) |
| 89 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) |
| 90 | #define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS) |
| 91 | #define AT91_DMA (0xffffec00 - AT91_BASE_SYS) |
| 92 | #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) |
| 93 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) |
| 94 | #define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) |
| 95 | #define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) |
| 96 | #define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) |
| 97 | #define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) |
| 98 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
| 99 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) |
| 100 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) |
| 101 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) |
| 102 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) |
| 103 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) |
| 104 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) |
| 105 | |
| 106 | #define AT91_USART0 AT91CAP9_BASE_US0 |
| 107 | #define AT91_USART1 AT91CAP9_BASE_US1 |
| 108 | #define AT91_USART2 AT91CAP9_BASE_US2 |
| 109 | |
| Stelian Pop | 048bcfb | 2008-03-26 19:52:30 +0100 | [diff] [blame] | 110 | /* |
| 111 | * Internal Memory. |
| 112 | */ |
| 113 | #define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */ |
| 114 | #define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */ |
| 115 | |
| 116 | #define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */ |
| 117 | #define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */ |
| 118 | |
| 119 | #define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */ |
| 120 | #define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */ |
| 121 | #define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */ |
| 122 | |
| 123 | #define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 |
| 124 | |
| 125 | #endif |