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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Philipp Tomsichdf48c792017-05-31 17:59:34 +02002/*
3 * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
Philipp Tomsichdf48c792017-05-31 17:59:34 +02004 */
5
6#include <common.h>
7#include <clk.h>
8#include <display.h>
9#include <dm.h>
10#include <dw_hdmi.h>
11#include <edid.h>
12#include <regmap.h>
13#include <syscon.h>
14#include <asm/gpio.h>
Kever Yang9fbe17c2019-03-28 11:01:23 +080015#include <asm/arch-rockchip/clock.h>
16#include <asm/arch-rockchip/hardware.h>
17#include <asm/arch-rockchip/grf_rk3399.h>
Philipp Tomsichdf48c792017-05-31 17:59:34 +020018#include <power/regulator.h>
19#include "rk_hdmi.h"
20
21static int rk3399_hdmi_enable(struct udevice *dev, int panel_bpp,
22 const struct display_timing *edid)
23{
24 struct rk_hdmi_priv *priv = dev_get_priv(dev);
Simon Glass71fa5b42020-12-03 16:55:18 -070025 struct display_plat *uc_plat = dev_get_uclass_plat(dev);
Philipp Tomsichdf48c792017-05-31 17:59:34 +020026 int vop_id = uc_plat->source_id;
27 struct rk3399_grf_regs *grf = priv->grf;
28
29 /* select the hdmi encoder input data from our source_id */
30 rk_clrsetreg(&grf->soc_con20, GRF_RK3399_HDMI_VOP_SEL_MASK,
31 (vop_id == 1) ? GRF_RK3399_HDMI_VOP_SEL_L : 0);
32
33 return dw_hdmi_enable(&priv->hdmi, edid);
34}
35
Simon Glassaad29ae2020-12-03 16:55:21 -070036static int rk3399_hdmi_of_to_plat(struct udevice *dev)
Philipp Tomsichdf48c792017-05-31 17:59:34 +020037{
38 struct rk_hdmi_priv *priv = dev_get_priv(dev);
39 struct dw_hdmi *hdmi = &priv->hdmi;
40
41 hdmi->i2c_clk_high = 0x7a;
42 hdmi->i2c_clk_low = 0x8d;
43
Simon Glassaad29ae2020-12-03 16:55:21 -070044 return rk_hdmi_of_to_plat(dev);
Philipp Tomsichdf48c792017-05-31 17:59:34 +020045}
46
47static const char * const rk3399_regulator_names[] = {
48 "vcc1v8_hdmi",
49 "vcc0v9_hdmi"
50};
51
52static int rk3399_hdmi_probe(struct udevice *dev)
53{
54 /* Enable regulators required for HDMI */
55 rk_hdmi_probe_regulators(dev, rk3399_regulator_names,
56 ARRAY_SIZE(rk3399_regulator_names));
57
58 return rk_hdmi_probe(dev);
59}
60
61static const struct dm_display_ops rk3399_hdmi_ops = {
62 .read_edid = rk_hdmi_read_edid,
63 .enable = rk3399_hdmi_enable,
64};
65
66static const struct udevice_id rk3399_hdmi_ids[] = {
67 { .compatible = "rockchip,rk3399-dw-hdmi" },
68 { }
69};
70
71U_BOOT_DRIVER(rk3399_hdmi_rockchip) = {
72 .name = "rk3399_hdmi_rockchip",
73 .id = UCLASS_DISPLAY,
74 .of_match = rk3399_hdmi_ids,
75 .ops = &rk3399_hdmi_ops,
Simon Glassaad29ae2020-12-03 16:55:21 -070076 .of_to_plat = rk3399_hdmi_of_to_plat,
Philipp Tomsichdf48c792017-05-31 17:59:34 +020077 .probe = rk3399_hdmi_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -070078 .priv_auto = sizeof(struct rk_hdmi_priv),
Philipp Tomsichdf48c792017-05-31 17:59:34 +020079};