blob: 027fdd37da3b6b4827d73f23554e5261166fd912 [file] [log] [blame]
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +01001// SPDX-License-Identifier: GPL-2.0+
2
3#include <common.h>
4#include <asm/io.h>
5#include <memalign.h>
6#include <nand.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -06007#include <linux/bitops.h>
Simon Glassd66c5f72020-02-03 07:36:15 -07008#include <linux/err.h>
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +01009#include <linux/errno.h>
10#include <linux/io.h>
11#include <linux/ioport.h>
12#include <dm.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060013#include <linux/printk.h>
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +010014
15#include "brcmnand.h"
16
17struct bcm6858_nand_soc {
18 struct brcmnand_soc soc;
19 void __iomem *base;
20};
21
22#define BCM6858_NAND_INT 0x00
23#define BCM6858_NAND_STATUS_SHIFT 0
24#define BCM6858_NAND_STATUS_MASK (0xfff << BCM6858_NAND_STATUS_SHIFT)
25
26#define BCM6858_NAND_INT_EN 0x04
27#define BCM6858_NAND_ENABLE_SHIFT 0
28#define BCM6858_NAND_ENABLE_MASK (0xffff << BCM6858_NAND_ENABLE_SHIFT)
29
30enum {
31 BCM6858_NP_READ = BIT(0),
32 BCM6858_BLOCK_ERASE = BIT(1),
33 BCM6858_COPY_BACK = BIT(2),
34 BCM6858_PAGE_PGM = BIT(3),
35 BCM6858_CTRL_READY = BIT(4),
36 BCM6858_DEV_RBPIN = BIT(5),
37 BCM6858_ECC_ERR_UNC = BIT(6),
38 BCM6858_ECC_ERR_CORR = BIT(7),
39};
40
41static bool bcm6858_nand_intc_ack(struct brcmnand_soc *soc)
42{
43 struct bcm6858_nand_soc *priv =
44 container_of(soc, struct bcm6858_nand_soc, soc);
45 void __iomem *mmio = priv->base + BCM6858_NAND_INT;
46 u32 val = brcmnand_readl(mmio);
47
48 if (val & (BCM6858_CTRL_READY << BCM6858_NAND_STATUS_SHIFT)) {
49 /* Ack interrupt */
50 val &= ~BCM6858_NAND_STATUS_MASK;
51 val |= BCM6858_CTRL_READY << BCM6858_NAND_STATUS_SHIFT;
52 brcmnand_writel(val, mmio);
53 return true;
54 }
55
56 return false;
57}
58
59static void bcm6858_nand_intc_set(struct brcmnand_soc *soc, bool en)
60{
61 struct bcm6858_nand_soc *priv =
62 container_of(soc, struct bcm6858_nand_soc, soc);
63 void __iomem *mmio = priv->base + BCM6858_NAND_INT_EN;
64 u32 val = brcmnand_readl(mmio);
65
66 /* Don't ack any interrupts */
67 val &= ~BCM6858_NAND_STATUS_MASK;
68
69 if (en)
70 val |= BCM6858_CTRL_READY << BCM6858_NAND_ENABLE_SHIFT;
71 else
72 val &= ~(BCM6858_CTRL_READY << BCM6858_NAND_ENABLE_SHIFT);
73
74 brcmnand_writel(val, mmio);
75}
76
77static int bcm6858_nand_probe(struct udevice *dev)
78{
79 struct udevice *pdev = dev;
80 struct bcm6858_nand_soc *priv = dev_get_priv(dev);
81 struct brcmnand_soc *soc;
82 struct resource res;
83
84 soc = &priv->soc;
85
86 dev_read_resource_byname(pdev, "nand-int-base", &res);
87 priv->base = devm_ioremap(dev, res.start, resource_size(&res));
88 if (IS_ERR(priv->base))
89 return PTR_ERR(priv->base);
90
91 soc->ctlrdy_ack = bcm6858_nand_intc_ack;
92 soc->ctlrdy_set_enabled = bcm6858_nand_intc_set;
93
94 /* Disable and ack all interrupts */
95 brcmnand_writel(0, priv->base + BCM6858_NAND_INT_EN);
96 brcmnand_writel(0, priv->base + BCM6858_NAND_INT);
97
98 return brcmnand_probe(pdev, soc);
99}
100
101static const struct udevice_id bcm6858_nand_dt_ids[] = {
102 {
103 .compatible = "brcm,nand-bcm6858",
104 },
105 { /* sentinel */ }
106};
107
108U_BOOT_DRIVER(bcm6858_nand) = {
109 .name = "bcm6858-nand",
110 .id = UCLASS_MTD,
111 .of_match = bcm6858_nand_dt_ids,
112 .probe = bcm6858_nand_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700113 .priv_auto = sizeof(struct bcm6858_nand_soc),
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100114};
115
116void board_nand_init(void)
117{
118 struct udevice *dev;
119 int ret;
120
121 ret = uclass_get_device_by_driver(UCLASS_MTD,
Simon Glass65130cd2020-12-28 20:34:56 -0700122 DM_DRIVER_GET(bcm6858_nand), &dev);
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100123 if (ret && ret != -ENODEV)
124 pr_err("Failed to initialize %s. (error %d)\n", dev->name,
125 ret);
126}