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git01.mediatek.com / filogic / uboot / d53a74afccbf450d6f50df0dbb8bb9cf80061e7a / . / include / configs / theadorable.h
blob: 587b134a1b36ea851141e8196a490767b2969f70 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]2/*
3 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]4 */
5
6#ifndef _CONFIG_THEADORABLE_H
7#define _CONFIG_THEADORABLE_H
8
9/*
10 * High Level Configuration Options (easy to change)
11 */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]12
13/*
14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
15 * for DDR ECC byte filling in the SPL before loading the main
16 * U-Boot into it.
17 */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]18#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
19
20/*
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]21 * The debugging version enables USB support via defconfig.
22 * This version should also enable all other non-production
23 * interfaces / features.
24 */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]25
26/* I2C */
27#define CONFIG_SYS_I2C
28#define CONFIG_SYS_I2C_MVTWSI
29#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Stefan Roese07b5e042016-04-08 15:58:29 +0200[diff] [blame]30#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]31#define CONFIG_SYS_I2C_SLAVE 0x0
32#define CONFIG_SYS_I2C_SPEED 100000
33
34/* USB/EHCI configuration */
35#define CONFIG_EHCI_IS_TDI
36#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
37
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]38/* Environment in SPI NOR flash */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]39
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]40#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
41
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]42/* Keep device tree and initrd in lower memory so the kernel can access them */
43#define CONFIG_EXTRA_ENV_SETTINGS \
44 "fdt_high=0x10000000\0" \
45 "initrd_high=0x10000000\0"
46
47/* SATA support */
48#define CONFIG_SYS_SATA_MAX_DEVICE 1
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]49#define CONFIG_LBA48
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]50
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]51/* Enable LCD and reserve 512KB from top of memory*/
52#define CONFIG_SYS_MEM_TOP_HIDE 0x80000
53
Stefan Roesef0547582016-02-12 14:24:07 +0100[diff] [blame]54/* FPGA programming support */
Stefan Roesef0547582016-02-12 14:24:07 +0100[diff] [blame]55#define CONFIG_FPGA_STRATIX_V
56
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]57/*
Stefan Roese1a4e9802016-04-07 10:48:14 +0200[diff] [blame]58 * Bootcounter
59 */
Stefan Roese1a4e9802016-04-07 10:48:14 +0200[diff] [blame]60/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
61#define BOOTCOUNT_ADDR 0x1000
62
63/*
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]64 * mv-common.h should be defined after CMD configs since it used them
65 * to enable certain macros
66 */
67#include "mv-common.h"
68
69/*
70 * Memory layout while starting into the bin_hdr via the
71 * BootROM:
72 *
73 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
74 * 0x4000.4030 bin_hdr start address
75 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
76 * 0x4007.fffc BootROM stack top
77 *
78 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
79 * L2 cache thus cannot be used.
80 */
81
82/* SPL */
83/* Defines for SPL */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]84#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
85
86#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
87#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
88
89#ifdef CONFIG_SPL_BUILD
90#define CONFIG_SYS_MALLOC_SIMPLE
91#endif
92
93#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
94#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
95
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]96/* SPL related SPI defines */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]97#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
98
99/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
100#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
101
102#endif /* _CONFIG_THEADORABLE_H */