Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | d9050b5 | 2015-04-20 12:37:23 -0600 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2015 Google, Inc |
| 4 | * Written by Simon Glass <sjg@chromium.org> |
Simon Glass | d9050b5 | 2015-04-20 12:37:23 -0600 | [diff] [blame] | 5 | */ |
| 6 | |
Patrick Delaunay | 8131335 | 2021-04-27 11:02:19 +0200 | [diff] [blame] | 7 | #define LOG_CATEGORY UCLASS_RTC |
| 8 | |
Simon Glass | d9050b5 | 2015-04-20 12:37:23 -0600 | [diff] [blame] | 9 | #include <dm.h> |
| 10 | #include <errno.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 11 | #include <log.h> |
Simon Glass | d9050b5 | 2015-04-20 12:37:23 -0600 | [diff] [blame] | 12 | #include <rtc.h> |
| 13 | |
| 14 | int dm_rtc_get(struct udevice *dev, struct rtc_time *time) |
| 15 | { |
| 16 | struct rtc_ops *ops = rtc_get_ops(dev); |
| 17 | |
| 18 | assert(ops); |
| 19 | if (!ops->get) |
| 20 | return -ENOSYS; |
| 21 | return ops->get(dev, time); |
| 22 | } |
| 23 | |
| 24 | int dm_rtc_set(struct udevice *dev, struct rtc_time *time) |
| 25 | { |
| 26 | struct rtc_ops *ops = rtc_get_ops(dev); |
| 27 | |
| 28 | assert(ops); |
| 29 | if (!ops->set) |
| 30 | return -ENOSYS; |
| 31 | return ops->set(dev, time); |
| 32 | } |
| 33 | |
| 34 | int dm_rtc_reset(struct udevice *dev) |
| 35 | { |
| 36 | struct rtc_ops *ops = rtc_get_ops(dev); |
| 37 | |
| 38 | assert(ops); |
| 39 | if (!ops->reset) |
| 40 | return -ENOSYS; |
| 41 | return ops->reset(dev); |
| 42 | } |
| 43 | |
Rasmus Villemoes | b9e40a2 | 2020-07-06 22:01:10 +0200 | [diff] [blame] | 44 | int dm_rtc_read(struct udevice *dev, unsigned int reg, u8 *buf, unsigned int len) |
| 45 | { |
| 46 | struct rtc_ops *ops = rtc_get_ops(dev); |
| 47 | |
| 48 | assert(ops); |
| 49 | if (ops->read) |
| 50 | return ops->read(dev, reg, buf, len); |
| 51 | if (!ops->read8) |
| 52 | return -ENOSYS; |
| 53 | while (len--) { |
| 54 | int ret = ops->read8(dev, reg++); |
| 55 | |
| 56 | if (ret < 0) |
| 57 | return ret; |
| 58 | *buf++ = ret; |
| 59 | } |
| 60 | return 0; |
| 61 | } |
| 62 | |
Rasmus Villemoes | 579c992 | 2020-07-06 22:01:11 +0200 | [diff] [blame] | 63 | int dm_rtc_write(struct udevice *dev, unsigned int reg, |
| 64 | const u8 *buf, unsigned int len) |
| 65 | { |
| 66 | struct rtc_ops *ops = rtc_get_ops(dev); |
| 67 | |
| 68 | assert(ops); |
| 69 | if (ops->write) |
| 70 | return ops->write(dev, reg, buf, len); |
| 71 | if (!ops->write8) |
| 72 | return -ENOSYS; |
| 73 | while (len--) { |
| 74 | int ret = ops->write8(dev, reg++, *buf++); |
| 75 | |
| 76 | if (ret < 0) |
| 77 | return ret; |
| 78 | } |
| 79 | return 0; |
| 80 | } |
| 81 | |
Simon Glass | d9050b5 | 2015-04-20 12:37:23 -0600 | [diff] [blame] | 82 | int rtc_read8(struct udevice *dev, unsigned int reg) |
| 83 | { |
| 84 | struct rtc_ops *ops = rtc_get_ops(dev); |
| 85 | |
| 86 | assert(ops); |
Rasmus Villemoes | 6f0854e | 2020-07-06 22:01:12 +0200 | [diff] [blame] | 87 | if (ops->read8) |
| 88 | return ops->read8(dev, reg); |
| 89 | if (ops->read) { |
| 90 | u8 buf[1]; |
| 91 | int ret = ops->read(dev, reg, buf, 1); |
| 92 | |
| 93 | if (ret < 0) |
| 94 | return ret; |
| 95 | return buf[0]; |
| 96 | } |
| 97 | return -ENOSYS; |
Simon Glass | d9050b5 | 2015-04-20 12:37:23 -0600 | [diff] [blame] | 98 | } |
| 99 | |
| 100 | int rtc_write8(struct udevice *dev, unsigned int reg, int val) |
| 101 | { |
| 102 | struct rtc_ops *ops = rtc_get_ops(dev); |
| 103 | |
| 104 | assert(ops); |
Rasmus Villemoes | 6f0854e | 2020-07-06 22:01:12 +0200 | [diff] [blame] | 105 | if (ops->write8) |
| 106 | return ops->write8(dev, reg, val); |
| 107 | if (ops->write) { |
| 108 | u8 buf[1] = { val }; |
| 109 | |
| 110 | return ops->write(dev, reg, buf, 1); |
| 111 | } |
| 112 | return -ENOSYS; |
Simon Glass | d9050b5 | 2015-04-20 12:37:23 -0600 | [diff] [blame] | 113 | } |
| 114 | |
Bin Meng | fbfe53d | 2017-03-16 07:26:27 -0700 | [diff] [blame] | 115 | int rtc_read16(struct udevice *dev, unsigned int reg, u16 *valuep) |
| 116 | { |
| 117 | u16 value = 0; |
| 118 | int ret; |
| 119 | int i; |
| 120 | |
| 121 | for (i = 0; i < sizeof(value); i++) { |
| 122 | ret = rtc_read8(dev, reg + i); |
| 123 | if (ret < 0) |
| 124 | return ret; |
| 125 | value |= ret << (i << 3); |
| 126 | } |
| 127 | |
| 128 | *valuep = value; |
| 129 | return 0; |
| 130 | } |
| 131 | |
| 132 | int rtc_write16(struct udevice *dev, unsigned int reg, u16 value) |
| 133 | { |
| 134 | int i, ret; |
| 135 | |
| 136 | for (i = 0; i < sizeof(value); i++) { |
| 137 | ret = rtc_write8(dev, reg + i, (value >> (i << 3)) & 0xff); |
| 138 | if (ret) |
| 139 | return ret; |
| 140 | } |
| 141 | |
| 142 | return 0; |
| 143 | } |
| 144 | |
Simon Glass | d9050b5 | 2015-04-20 12:37:23 -0600 | [diff] [blame] | 145 | int rtc_read32(struct udevice *dev, unsigned int reg, u32 *valuep) |
| 146 | { |
| 147 | u32 value = 0; |
| 148 | int ret; |
| 149 | int i; |
| 150 | |
| 151 | for (i = 0; i < sizeof(value); i++) { |
| 152 | ret = rtc_read8(dev, reg + i); |
Simon Glass | c60a5bc | 2015-10-18 15:55:31 -0600 | [diff] [blame] | 153 | if (ret < 0) |
Simon Glass | d9050b5 | 2015-04-20 12:37:23 -0600 | [diff] [blame] | 154 | return ret; |
| 155 | value |= ret << (i << 3); |
| 156 | } |
| 157 | |
| 158 | *valuep = value; |
| 159 | return 0; |
| 160 | } |
| 161 | |
| 162 | int rtc_write32(struct udevice *dev, unsigned int reg, u32 value) |
| 163 | { |
| 164 | int i, ret; |
| 165 | |
| 166 | for (i = 0; i < sizeof(value); i++) { |
| 167 | ret = rtc_write8(dev, reg + i, (value >> (i << 3)) & 0xff); |
| 168 | if (ret) |
| 169 | return ret; |
| 170 | } |
| 171 | |
| 172 | return 0; |
| 173 | } |
| 174 | |
| 175 | UCLASS_DRIVER(rtc) = { |
| 176 | .name = "rtc", |
| 177 | .id = UCLASS_RTC, |
Michal Simek | 13bbcf4 | 2021-07-29 12:57:12 +0200 | [diff] [blame] | 178 | .flags = DM_UC_FLAG_SEQ_ALIAS, |
Simon Glass | 9288265 | 2021-08-07 07:24:04 -0600 | [diff] [blame] | 179 | #if CONFIG_IS_ENABLED(OF_REAL) |
Simon Glass | 302ea78 | 2018-11-18 08:14:35 -0700 | [diff] [blame] | 180 | .post_bind = dm_scan_fdt_dev, |
Simon Glass | e45710b | 2020-10-03 11:31:34 -0600 | [diff] [blame] | 181 | #endif |
Simon Glass | d9050b5 | 2015-04-20 12:37:23 -0600 | [diff] [blame] | 182 | }; |