| Icenowy Zheng | 8701e10 | 2022-01-29 10:23:04 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * suniv DRAM controller register definition |
| 4 | * |
| 5 | * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io> |
| 6 | * |
| 7 | * Based on xboot's arch/arm32/mach-f1c100s/sys-dram.c, which is: |
| 8 | * |
| 9 | * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com> |
| 10 | */ |
| 11 | |
| 12 | #define PIO_SDRAM_DRV (0x2c0) |
| 13 | #define PIO_SDRAM_PULL (0x2c4) |
| 14 | |
| 15 | #define DRAM_SCONR (0x00) |
| 16 | #define DRAM_STMG0R (0x04) |
| 17 | #define DRAM_STMG1R (0x08) |
| 18 | #define DRAM_SCTLR (0x0c) |
| 19 | #define DRAM_SREFR (0x10) |
| 20 | #define DRAM_SEXTMR (0x14) |
| 21 | #define DRAM_DDLYR (0x24) |
| 22 | #define DRAM_DADRR (0x28) |
| 23 | #define DRAM_DVALR (0x2c) |
| 24 | #define DRAM_DRPTR0 (0x30) |
| 25 | #define DRAM_DRPTR1 (0x34) |
| 26 | #define DRAM_DRPTR2 (0x38) |
| 27 | #define DRAM_DRPTR3 (0x3c) |
| 28 | #define DRAM_SEFR (0x40) |
| 29 | #define DRAM_MAE (0x44) |
| 30 | #define DRAM_ASPR (0x48) |
| 31 | #define DRAM_SDLY0 (0x4C) |
| 32 | #define DRAM_SDLY1 (0x50) |
| 33 | #define DRAM_SDLY2 (0x54) |
| 34 | #define DRAM_MCR0 (0x100) |
| 35 | #define DRAM_MCR1 (0x104) |
| 36 | #define DRAM_MCR2 (0x108) |
| 37 | #define DRAM_MCR3 (0x10c) |
| 38 | #define DRAM_MCR4 (0x110) |
| 39 | #define DRAM_MCR5 (0x114) |
| 40 | #define DRAM_MCR6 (0x118) |
| 41 | #define DRAM_MCR7 (0x11c) |
| 42 | #define DRAM_MCR8 (0x120) |
| 43 | #define DRAM_MCR9 (0x124) |
| 44 | #define DRAM_MCR10 (0x128) |
| 45 | #define DRAM_MCR11 (0x12c) |
| 46 | #define DRAM_BWCR (0x140) |