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git01.mediatek.com / filogic / uboot / d4f79cbc547efb4dd11ee2867dbf74445a67cc98 / . / drivers / gpio / npcm_gpio.c
blob: 8afd57fa8e5364d0822d6306594aeaf043e3c0c5 [file] [log] [blame]
Stanley Chu71d1ed02022-02-25 10:14:50 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2022 Nuvoton Technology Corp.
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <asm/gpio.h>
9#include <linux/io.h>
10
11#define NPCM_GPIOS_PER_BANK 32
12
13/* Register offsets */
14#define GPIO_DIN 0x4 /* RO - Data In */
15#define GPIO_DOUT 0xC /* RW - Data Out */
16#define GPIO_OE 0x10 /* RW - Output Enable */
17#define GPIO_IEM 0x58 /* RW - Input Enable Mask */
18#define GPIO_OES 0x70 /* WO - Output Enable Register Set */
19#define GPIO_OEC 0x74 /* WO - Output Enable Register Clear */
20
21struct npcm_gpio_priv {
22 void __iomem *base;
23};
24
25static int npcm_gpio_direction_input(struct udevice *dev, unsigned int offset)
26{
27 struct npcm_gpio_priv *priv = dev_get_priv(dev);
28
29 writel(BIT(offset), priv->base + GPIO_OEC);
30 setbits_le32(priv->base + GPIO_IEM, BIT(offset));
31
32 return 0;
33}
34
35static int npcm_gpio_direction_output(struct udevice *dev, unsigned int offset,
36 int value)
37{
38 struct npcm_gpio_priv *priv = dev_get_priv(dev);
39
40 clrbits_le32(priv->base + GPIO_IEM, BIT(offset));
41 writel(BIT(offset), priv->base + GPIO_OES);
42
43 if (value)
44 setbits_le32(priv->base + GPIO_DOUT, BIT(offset));
45 else
46 clrbits_le32(priv->base + GPIO_DOUT, BIT(offset));
47
48 return 0;
49}
50
51static int npcm_gpio_get_value(struct udevice *dev, unsigned int offset)
52{
53 struct npcm_gpio_priv *priv = dev_get_priv(dev);
54
55 if (readl(priv->base + GPIO_IEM) & BIT(offset))
56 return !!(readl(priv->base + GPIO_DIN) & BIT(offset));
57
58 if (readl(priv->base + GPIO_OE) & BIT(offset))
59 return !!(readl(priv->base + GPIO_DOUT) & BIT(offset));
60
61 return -EINVAL;
62}
63
64static int npcm_gpio_set_value(struct udevice *dev, unsigned int offset,
65 int value)
66{
67 struct npcm_gpio_priv *priv = dev_get_priv(dev);
68
69 if (value)
70 setbits_le32(priv->base + GPIO_DOUT, BIT(offset));
71 else
72 clrbits_le32(priv->base + GPIO_DOUT, BIT(offset));
73
74 return 0;
75}
76
77static int npcm_gpio_get_function(struct udevice *dev, unsigned int offset)
78{
79 struct npcm_gpio_priv *priv = dev_get_priv(dev);
80
81 if (readl(priv->base + GPIO_IEM) & BIT(offset))
82 return GPIOF_INPUT;
83
84 if (readl(priv->base + GPIO_OE) & BIT(offset))
85 return GPIOF_OUTPUT;
86
87 return GPIOF_FUNC;
88}
89
90static const struct dm_gpio_ops npcm_gpio_ops = {
91 .direction_input = npcm_gpio_direction_input,
92 .direction_output = npcm_gpio_direction_output,
93 .get_value = npcm_gpio_get_value,
94 .set_value = npcm_gpio_set_value,
95 .get_function = npcm_gpio_get_function,
96};
97
98static int npcm_gpio_probe(struct udevice *dev)
99{
100 struct npcm_gpio_priv *priv = dev_get_priv(dev);
101 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
102
103 priv->base = dev_read_addr_ptr(dev);
104 uc_priv->gpio_count = NPCM_GPIOS_PER_BANK;
105 uc_priv->bank_name = dev->name;
106
107 return 0;
108}
109
110static const struct udevice_id npcm_gpio_match[] = {
111 { .compatible = "nuvoton,npcm845-gpio" },
112 { .compatible = "nuvoton,npcm750-gpio" },
113 { }
114};
115
116U_BOOT_DRIVER(npcm_gpio) = {
117 .name = "npcm_gpio",
118 .id = UCLASS_GPIO,
119 .of_match = npcm_gpio_match,
120 .probe = npcm_gpio_probe,
121 .priv_auto = sizeof(struct npcm_gpio_priv),
122 .ops = &npcm_gpio_ops,
123};