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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: Intel */
Bin Meng2922b3e2014-12-12 21:05:28 +08002/*
3 * Copyright (C) 2013, Intel Corporation
4 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
Bin Meng2922b3e2014-12-12 21:05:28 +08005 */
6
7#ifndef _FSP_HEADER_H_
8#define _FSP_HEADER_H_
9
10#define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */
11
Bin Mengdb60d862014-12-17 15:50:49 +080012struct __packed fsp_header {
Bin Meng2922b3e2014-12-12 21:05:28 +080013 u32 sign; /* 'FSPH' */
14 u32 hdr_len; /* header length */
15 u8 reserved1[3];
16 u8 hdr_rev; /* header rev */
17 u32 img_rev; /* image rev */
18 char img_id[8]; /* signature string */
19 u32 img_size; /* image size */
20 u32 img_base; /* image base */
21 u32 img_attr; /* image attribute */
22 u32 cfg_region_off; /* configuration region offset */
23 u32 cfg_region_size; /* configuration region size */
24 u32 api_num; /* number of API entries */
25 u32 fsp_tempram_init; /* tempram_init offset */
26 u32 fsp_init; /* fsp_init offset */
27 u32 fsp_notify; /* fsp_notify offset */
Bin Mengc23720c2017-08-15 22:41:57 -070028 u32 fsp_mem_init; /* fsp_mem_init offset */
29 u32 fsp_tempram_exit; /* fsp_tempram_exit offset */
30 u32 fsp_silicon_init; /* fsp_silicon_init offset */
Bin Meng2922b3e2014-12-12 21:05:28 +080031};
32
Bin Mengc23720c2017-08-15 22:41:57 -070033#define FSP_HEADER_REVISION_1 1
34#define FSP_HEADER_REVISION_2 2
35
Simon Glass99bb2012019-09-25 08:11:33 -060036enum fsp_type {
37 FSP_ATTR_COMP_TYPE_FSP_T = 1,
38 FSP_ATTR_COMP_TYPE_FSP_M = 2,
39 FSP_ATTR_COMP_TYPE_FSP_S = 3,
40};
41
42enum {
43 FSP_ATTR_GRAPHICS_SUPPORT = 1 << 0,
44 FSP_ATTR_COMP_TYPE_SHIFT = 28,
45 FSP_ATTR_COMP_TYPE_MASK = 0xfU << FSP_ATTR_COMP_TYPE_SHIFT,
46
47};
48
49#define EFI_FSPH_SIGNATURE SIGNATURE_32('F', 'S', 'P', 'H')
Bin Mengc23720c2017-08-15 22:41:57 -070050
Bin Meng2922b3e2014-12-12 21:05:28 +080051#endif