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git01.mediatek.com / filogic / uboot / d4d97b0fdb4fee2e51a4a837230b6d9d10f4f480 / . / arch / arm / dts / imx53.dtsi
blob: e13009c8708b51c1b8811ca4dea64febc12d79a2 [file] [log] [blame]
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]1/*
2 * Copyright 2016 Beckhoff Automation
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#include "skeleton.dtsi"
15#include "imx53-pinfunc.h"
16#include <dt-bindings/clock/imx5-clock.h>
17#include <dt-bindings/gpio/gpio.h>
18#include <dt-bindings/input/input.h>
19#include <dt-bindings/interrupt-controller/irq.h>
20
21/ {
22 aliases {
23 serial1 = &uart2;
Lukasz Majewski5b696512018-04-26 13:18:00 +0200[diff] [blame]24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
28 gpio4 = &gpio5;
29 gpio5 = &gpio6;
30 gpio6 = &gpio7;
31 i2c0 = &i2c1;
32 i2c1 = &i2c2;
33 i2c2 = &i2c3;
Patrick Bruennd4d97b02019-01-03 07:54:33 +0100[diff] [blame^]34 mmc0 = &esdhc1;
35 mmc1 = &esdhc2;
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]36 };
37
Patrick Bruenn44b21332017-12-11 13:09:14 +0100[diff] [blame]38 tzic: tz-interrupt-controller@fffc000 {
39 compatible = "fsl,imx53-tzic", "fsl,tzic";
40 interrupt-controller;
41 #interrupt-cells = <1>;
42 reg = <0x0fffc000 0x4000>;
43 };
44
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]45 soc {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "simple-bus";
Patrick Bruenn44b21332017-12-11 13:09:14 +0100[diff] [blame]49 interrupt-parent = <&tzic>;
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]50 ranges;
51
52 aips@50000000 { /* AIPS1 */
53 compatible = "fsl,aips-bus", "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 reg = <0x50000000 0x10000000>;
57 ranges;
58
Patrick Bruennd4d97b02019-01-03 07:54:33 +0100[diff] [blame^]59 spba@50000000 {
60 compatible = "fsl,spba-bus", "simple-bus";
61 #address-cells = <1>;
62 #size-cells = <1>;
63 reg = <0x50000000 0x40000>;
64 ranges;
65
66 esdhc1: esdhc@50004000 {
67 compatible = "fsl,imx53-esdhc";
68 reg = <0x50004000 0x4000>;
69 interrupts = <1>;
70 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
71 <&clks IMX5_CLK_DUMMY>,
72 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
73 clock-names = "ipg", "ahb", "per";
74 bus-width = <4>;
75 status = "disabled";
76 };
77
78 esdhc2: esdhc@50008000 {
79 compatible = "fsl,imx53-esdhc";
80 reg = <0x50008000 0x4000>;
81 interrupts = <2>;
82 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
83 <&clks IMX5_CLK_DUMMY>,
84 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
85 clock-names = "ipg", "ahb", "per";
86 bus-width = <4>;
87 status = "disabled";
88 };
89 };
90
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]91 iomuxc: iomuxc@53fa8000 {
92 compatible = "fsl,imx53-iomuxc";
93 reg = <0x53fa8000 0x4000>;
94 };
95
96 gpr: iomuxc-gpr@53fa8000 {
97 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
98 reg = <0x53fa8000 0xc>;
99 };
100
101 uart2: serial@53fc0000 {
102 compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart";
103 reg = <0x53fc0000 0x4000>;
104 interrupts = <32>;
105 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
106 <&clks IMX5_CLK_UART2_PER_GATE>;
107 clock-names = "ipg", "per";
108 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
109 dma-names = "rx", "tx";
110 status = "disabled";
111 };
112
113 clks: ccm@53fd4000{
114 compatible = "fsl,imx53-ccm";
115 reg = <0x53fd4000 0x4000>;
116 interrupts = <0 71 0x04 0 72 0x04>;
117 #clock-cells = <1>;
118 };
119
Lukasz Majewski5b696512018-04-26 13:18:00 +0200[diff] [blame]120 gpio1: gpio@53f84000 {
121 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
122 reg = <0x53f84000 0x4000>;
123 interrupts = <50 51>;
124 gpio-controller;
125 #gpio-cells = <2>;
126 interrupt-controller;
127 #interrupt-cells = <2>;
128 };
129
130 gpio2: gpio@53f88000 {
131 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
132 reg = <0x53f88000 0x4000>;
133 interrupts = <52 53>;
134 gpio-controller;
135 #gpio-cells = <2>;
136 interrupt-controller;
137 #interrupt-cells = <2>;
138 };
139
140 gpio3: gpio@53f8c000 {
141 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
142 reg = <0x53f8c000 0x4000>;
143 interrupts = <54 55>;
144 gpio-controller;
145 #gpio-cells = <2>;
146 interrupt-controller;
147 #interrupt-cells = <2>;
148 };
149
150 gpio4: gpio@53f90000 {
151 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
152 reg = <0x53f90000 0x4000>;
153 interrupts = <56 57>;
154 gpio-controller;
155 #gpio-cells = <2>;
156 interrupt-controller;
157 #interrupt-cells = <2>;
158 };
159
160 gpio5: gpio@53fdc000 {
161 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
162 reg = <0x53fdc000 0x4000>;
163 interrupts = <103 104>;
164 gpio-controller;
165 #gpio-cells = <2>;
166 interrupt-controller;
167 #interrupt-cells = <2>;
168 };
169
170 gpio6: gpio@53fe0000 {
171 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
172 reg = <0x53fe0000 0x4000>;
173 interrupts = <105 106>;
174 gpio-controller;
175 #gpio-cells = <2>;
176 interrupt-controller;
177 #interrupt-cells = <2>;
178 };
179
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]180 gpio7: gpio@53fe4000 {
181 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
182 reg = <0x53fe4000 0x4000>;
183 interrupts = <107 108>;
184 gpio-controller;
185 #gpio-cells = <2>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 };
Lukasz Majewski5b696512018-04-26 13:18:00 +0200[diff] [blame]189
190 i2c3: i2c@53fec000 {
191 #address-cells = <1>;
192 #size-cells = <0>;
193 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
194 reg = <0x53fec000 0x4000>;
195 interrupts = <64>;
196 clocks = <&clks IMX5_CLK_I2C3_GATE>;
197 status = "disabled";
198 };
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]199 };
200
201 aips@60000000 { /* AIPS2 */
202 compatible = "fsl,aips-bus", "simple-bus";
203 #address-cells = <1>;
204 #size-cells = <1>;
205 reg = <0x60000000 0x10000000>;
206 ranges;
207
208 sdma: sdma@63fb0000 {
209 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
210 reg = <0x63fb0000 0x4000>;
211 interrupts = <6>;
212 clocks = <&clks IMX5_CLK_SDMA_GATE>,
213 <&clks IMX5_CLK_SDMA_GATE>;
214 clock-names = "ipg", "ahb";
215 #dma-cells = <3>;
216 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
217 };
218
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]219 fec: ethernet@63fec000 {
220 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
221 reg = <0x63fec000 0x4000>;
222 interrupts = <87>;
223 clocks = <&clks IMX5_CLK_FEC_GATE>,
224 <&clks IMX5_CLK_FEC_GATE>,
225 <&clks IMX5_CLK_FEC_GATE>;
226 clock-names = "ipg", "ahb", "ptp";
227 status = "disabled";
228 };
Lukasz Majewski5b696512018-04-26 13:18:00 +0200[diff] [blame]229
230 i2c2: i2c@63fc4000 {
231 #address-cells = <1>;
232 #size-cells = <0>;
233 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
234 reg = <0x63fc4000 0x4000>;
235 interrupts = <63>;
236 clocks = <&clks IMX5_CLK_I2C2_GATE>;
237 status = "disabled";
238 };
239
240 i2c1: i2c@63fc8000 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
244 reg = <0x63fc8000 0x4000>;
245 interrupts = <62>;
246 clocks = <&clks IMX5_CLK_I2C1_GATE>;
247 status = "disabled";
248 };
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]249 };
250 };
251};