blob: 17e1601e81444e4cf971ccd3ecc603504790d2bb [file] [log] [blame]
Alper Nebi Yasak53f20332020-10-22 22:43:13 +03001// SPDX-License-Identifier: GPL-2.0
Philipp Tomsich1a18f302017-05-31 17:59:31 +02002/*
3 * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
4 * Copyright (c) 2015 Google, Inc
5 * Copyright 2014 Rockchip Inc.
Philipp Tomsich1a18f302017-05-31 17:59:31 +02006 */
7
Philipp Tomsich1a18f302017-05-31 17:59:31 +02008#include <display.h>
9#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Philipp Tomsich1a18f302017-05-31 17:59:31 +020011#include <regmap.h>
12#include <video.h>
Kever Yang9fbe17c2019-03-28 11:01:23 +080013#include <asm/arch-rockchip/hardware.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060014#include <asm/global_data.h>
Philipp Tomsich1a18f302017-05-31 17:59:31 +020015#include "rk_vop.h"
16
17DECLARE_GLOBAL_DATA_PTR;
18
19static void rk3399_set_pin_polarity(struct udevice *dev,
20 enum vop_modes mode, u32 polarity)
21{
22 struct rk_vop_priv *priv = dev_get_priv(dev);
23 struct rk3288_vop *regs = priv->regs;
24
25 /*
26 * The RK3399 VOPs (v3.5 and v3.6) require a per-mode setting of
27 * the polarity configuration (in ctrl1).
28 */
29 switch (mode) {
30 case VOP_MODE_HDMI:
31 clrsetbits_le32(&regs->dsp_ctrl1,
32 M_RK3399_DSP_HDMI_POL,
33 V_RK3399_DSP_HDMI_POL(polarity));
34 break;
35
36 case VOP_MODE_EDP:
37 clrsetbits_le32(&regs->dsp_ctrl1,
38 M_RK3399_DSP_EDP_POL,
39 V_RK3399_DSP_EDP_POL(polarity));
40 break;
41
42 case VOP_MODE_MIPI:
43 clrsetbits_le32(&regs->dsp_ctrl1,
44 M_RK3399_DSP_MIPI_POL,
45 V_RK3399_DSP_MIPI_POL(polarity));
46 break;
47
Philipp Tomsich1a18f302017-05-31 17:59:31 +020048 default:
49 debug("%s: unsupported output mode %x\n", __func__, mode);
50 }
51}
52
53/*
54 * Try some common regulators. We should really get these from the
55 * device tree somehow.
56 */
57static const char * const rk3399_regulator_names[] = {
58 "vcc33_lcd"
59};
60
61static int rk3399_vop_probe(struct udevice *dev)
62{
63 /* Before relocation we don't need to do anything */
64 if (!(gd->flags & GD_FLG_RELOC))
65 return 0;
66
67 /* Probe regulators required for the RK3399 VOP */
68 rk_vop_probe_regulators(dev, rk3399_regulator_names,
69 ARRAY_SIZE(rk3399_regulator_names));
70
71 return rk_vop_probe(dev);
72}
73
74struct rkvop_driverdata rk3399_lit_driverdata = {
75 .set_pin_polarity = rk3399_set_pin_polarity,
76};
77
78struct rkvop_driverdata rk3399_big_driverdata = {
79 .features = VOP_FEATURE_OUTPUT_10BIT,
80 .set_pin_polarity = rk3399_set_pin_polarity,
81};
82
83static const struct udevice_id rk3399_vop_ids[] = {
84 { .compatible = "rockchip,rk3399-vop-big",
85 .data = (ulong)&rk3399_big_driverdata },
86 { .compatible = "rockchip,rk3399-vop-lit",
87 .data = (ulong)&rk3399_lit_driverdata },
88 { }
89};
90
91static const struct video_ops rk3399_vop_ops = {
92};
93
94U_BOOT_DRIVER(rk3399_vop) = {
95 .name = "rk3399_vop",
96 .id = UCLASS_VIDEO,
97 .of_match = rk3399_vop_ids,
98 .ops = &rk3399_vop_ops,
99 .bind = rk_vop_bind,
100 .probe = rk3399_vop_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700101 .priv_auto = sizeof(struct rk_vop_priv),
Philipp Tomsich1a18f302017-05-31 17:59:31 +0200102};