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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Przemyslaw Marczak3753f282015-04-20 20:07:48 +02002/*
3 * Copyright (C) 2015 Samsung Electronics
4 *
5 * Przemyslaw Marczak <p.marczak@samsung.com>
Przemyslaw Marczak3753f282015-04-20 20:07:48 +02006 */
7
Philippe Schenkercdd4bfe2022-04-08 10:07:10 +02008#include <clk.h>
Przemyslaw Marczak3753f282015-04-20 20:07:48 +02009#include <errno.h>
10#include <dm.h>
Philippe Schenkercdd4bfe2022-04-08 10:07:10 +020011#include <linux/delay.h>
Simon Glass0f2af882020-05-10 11:40:05 -060012#include <log.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060013#include <asm/gpio.h>
Przemyslaw Marczak3753f282015-04-20 20:07:48 +020014#include <power/pmic.h>
15#include <power/regulator.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060016#include "regulator_common.h"
Przemyslaw Marczak3753f282015-04-20 20:07:48 +020017
Simon Glass1c1ddf62020-07-19 10:15:44 -060018#include "regulator_common.h"
19
Philippe Schenkercdd4bfe2022-04-08 10:07:10 +020020struct fixed_clock_regulator_plat {
21 struct clk *enable_clock;
22 unsigned int clk_enable_counter;
23};
24
Simon Glassaad29ae2020-12-03 16:55:21 -070025static int fixed_regulator_of_to_plat(struct udevice *dev)
Przemyslaw Marczak3753f282015-04-20 20:07:48 +020026{
Simon Glass71fa5b42020-12-03 16:55:18 -070027 struct dm_regulator_uclass_plat *uc_pdata;
Eugen Hristev81aa1922023-04-19 16:45:25 +030028 struct regulator_common_plat *plat;
Jonas Karlman7257f092023-07-22 13:30:21 +000029 bool gpios;
Przemyslaw Marczak3753f282015-04-20 20:07:48 +020030
Eugen Hristev81aa1922023-04-19 16:45:25 +030031 plat = dev_get_plat(dev);
Simon Glass71fa5b42020-12-03 16:55:18 -070032 uc_pdata = dev_get_uclass_plat(dev);
Przemyslaw Marczak3753f282015-04-20 20:07:48 +020033 if (!uc_pdata)
34 return -ENXIO;
35
Przemyslaw Marczak3753f282015-04-20 20:07:48 +020036 uc_pdata->type = REGULATOR_TYPE_FIXED;
37
Jonas Karlman7257f092023-07-22 13:30:21 +000038 gpios = dev_read_bool(dev, "gpios");
39 return regulator_common_of_to_plat(dev, plat, gpios ? "gpios" : "gpio");
Przemyslaw Marczak3753f282015-04-20 20:07:48 +020040}
41
42static int fixed_regulator_get_value(struct udevice *dev)
43{
Simon Glass71fa5b42020-12-03 16:55:18 -070044 struct dm_regulator_uclass_plat *uc_pdata;
Przemyslaw Marczak3753f282015-04-20 20:07:48 +020045
Simon Glass71fa5b42020-12-03 16:55:18 -070046 uc_pdata = dev_get_uclass_plat(dev);
Przemyslaw Marczak3753f282015-04-20 20:07:48 +020047 if (!uc_pdata)
48 return -ENXIO;
49
50 if (uc_pdata->min_uV != uc_pdata->max_uV) {
51 debug("Invalid constraints for: %s\n", uc_pdata->name);
52 return -EINVAL;
53 }
54
55 return uc_pdata->min_uV;
56}
57
58static int fixed_regulator_get_current(struct udevice *dev)
59{
Simon Glass71fa5b42020-12-03 16:55:18 -070060 struct dm_regulator_uclass_plat *uc_pdata;
Przemyslaw Marczak3753f282015-04-20 20:07:48 +020061
Simon Glass71fa5b42020-12-03 16:55:18 -070062 uc_pdata = dev_get_uclass_plat(dev);
Przemyslaw Marczak3753f282015-04-20 20:07:48 +020063 if (!uc_pdata)
64 return -ENXIO;
65
66 if (uc_pdata->min_uA != uc_pdata->max_uA) {
67 debug("Invalid constraints for: %s\n", uc_pdata->name);
68 return -EINVAL;
69 }
70
71 return uc_pdata->min_uA;
72}
73
Keerthy8690d6a2017-06-13 09:53:46 +053074static int fixed_regulator_get_enable(struct udevice *dev)
Przemyslaw Marczak3753f282015-04-20 20:07:48 +020075{
Simon Glassfa20e932020-12-03 16:55:20 -070076 return regulator_common_get_enable(dev, dev_get_plat(dev));
Przemyslaw Marczak3753f282015-04-20 20:07:48 +020077}
78
79static int fixed_regulator_set_enable(struct udevice *dev, bool enable)
80{
Simon Glassfa20e932020-12-03 16:55:20 -070081 return regulator_common_set_enable(dev, dev_get_plat(dev), enable);
Przemyslaw Marczak3753f282015-04-20 20:07:48 +020082}
83
Philippe Schenkercdd4bfe2022-04-08 10:07:10 +020084static int fixed_clock_regulator_get_enable(struct udevice *dev)
85{
86 struct fixed_clock_regulator_plat *priv = dev_get_priv(dev);
87
88 return priv->clk_enable_counter > 0;
89}
90
91static int fixed_clock_regulator_set_enable(struct udevice *dev, bool enable)
92{
93 struct fixed_clock_regulator_plat *priv = dev_get_priv(dev);
Eugen Hristev81aa1922023-04-19 16:45:25 +030094 struct regulator_common_plat *plat = dev_get_plat(dev);
Philippe Schenkercdd4bfe2022-04-08 10:07:10 +020095 int ret = 0;
96
97 if (enable) {
98 ret = clk_enable(priv->enable_clock);
99 priv->clk_enable_counter++;
100 } else {
101 ret = clk_disable(priv->enable_clock);
102 priv->clk_enable_counter--;
103 }
104 if (ret)
105 return ret;
106
Eugen Hristev81aa1922023-04-19 16:45:25 +0300107 if (enable && plat->startup_delay_us)
108 udelay(plat->startup_delay_us);
Philippe Schenkercdd4bfe2022-04-08 10:07:10 +0200109
Eugen Hristev81aa1922023-04-19 16:45:25 +0300110 if (!enable && plat->off_on_delay_us)
111 udelay(plat->off_on_delay_us);
Philippe Schenkercdd4bfe2022-04-08 10:07:10 +0200112
113 return ret;
114}
115
Przemyslaw Marczak3753f282015-04-20 20:07:48 +0200116static const struct dm_regulator_ops fixed_regulator_ops = {
117 .get_value = fixed_regulator_get_value,
118 .get_current = fixed_regulator_get_current,
119 .get_enable = fixed_regulator_get_enable,
120 .set_enable = fixed_regulator_set_enable,
121};
122
Philippe Schenkercdd4bfe2022-04-08 10:07:10 +0200123static const struct dm_regulator_ops fixed_clock_regulator_ops = {
124 .get_enable = fixed_clock_regulator_get_enable,
125 .set_enable = fixed_clock_regulator_set_enable,
126};
127
Przemyslaw Marczak3753f282015-04-20 20:07:48 +0200128static const struct udevice_id fixed_regulator_ids[] = {
129 { .compatible = "regulator-fixed" },
130 { },
131};
132
Philippe Schenkercdd4bfe2022-04-08 10:07:10 +0200133static const struct udevice_id fixed_clock_regulator_ids[] = {
134 { .compatible = "regulator-fixed-clock" },
135 { },
136};
137
Walter Lozano2901ac62020-06-25 01:10:04 -0300138U_BOOT_DRIVER(regulator_fixed) = {
139 .name = "regulator_fixed",
Przemyslaw Marczak3753f282015-04-20 20:07:48 +0200140 .id = UCLASS_REGULATOR,
141 .ops = &fixed_regulator_ops,
142 .of_match = fixed_regulator_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -0700143 .of_to_plat = fixed_regulator_of_to_plat,
Philippe Schenkercdd4bfe2022-04-08 10:07:10 +0200144 .plat_auto = sizeof(struct regulator_common_plat),
145};
146
147U_BOOT_DRIVER(regulator_fixed_clock) = {
148 .name = "regulator_fixed_clk",
149 .id = UCLASS_REGULATOR,
150 .ops = &fixed_clock_regulator_ops,
151 .of_match = fixed_clock_regulator_ids,
152 .of_to_plat = fixed_regulator_of_to_plat,
153 .plat_auto = sizeof(struct fixed_clock_regulator_plat),
Przemyslaw Marczak3753f282015-04-20 20:07:48 +0200154};