Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015 Samsung Electronics |
| 4 | * |
| 5 | * Przemyslaw Marczak <p.marczak@samsung.com> |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
Philippe Schenker | cdd4bfe | 2022-04-08 10:07:10 +0200 | [diff] [blame] | 8 | #include <clk.h> |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 9 | #include <errno.h> |
| 10 | #include <dm.h> |
Philippe Schenker | cdd4bfe | 2022-04-08 10:07:10 +0200 | [diff] [blame] | 11 | #include <linux/delay.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 12 | #include <log.h> |
Simon Glass | bdd5f81 | 2023-09-14 18:21:46 -0600 | [diff] [blame] | 13 | #include <asm/gpio.h> |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 14 | #include <power/pmic.h> |
| 15 | #include <power/regulator.h> |
Simon Glass | bdd5f81 | 2023-09-14 18:21:46 -0600 | [diff] [blame] | 16 | #include "regulator_common.h" |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 17 | |
Simon Glass | 1c1ddf6 | 2020-07-19 10:15:44 -0600 | [diff] [blame] | 18 | #include "regulator_common.h" |
| 19 | |
Philippe Schenker | cdd4bfe | 2022-04-08 10:07:10 +0200 | [diff] [blame] | 20 | struct fixed_clock_regulator_plat { |
| 21 | struct clk *enable_clock; |
| 22 | unsigned int clk_enable_counter; |
| 23 | }; |
| 24 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 25 | static int fixed_regulator_of_to_plat(struct udevice *dev) |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 26 | { |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 27 | struct dm_regulator_uclass_plat *uc_pdata; |
Eugen Hristev | 81aa192 | 2023-04-19 16:45:25 +0300 | [diff] [blame] | 28 | struct regulator_common_plat *plat; |
Jonas Karlman | 7257f09 | 2023-07-22 13:30:21 +0000 | [diff] [blame] | 29 | bool gpios; |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 30 | |
Eugen Hristev | 81aa192 | 2023-04-19 16:45:25 +0300 | [diff] [blame] | 31 | plat = dev_get_plat(dev); |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 32 | uc_pdata = dev_get_uclass_plat(dev); |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 33 | if (!uc_pdata) |
| 34 | return -ENXIO; |
| 35 | |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 36 | uc_pdata->type = REGULATOR_TYPE_FIXED; |
| 37 | |
Jonas Karlman | 7257f09 | 2023-07-22 13:30:21 +0000 | [diff] [blame] | 38 | gpios = dev_read_bool(dev, "gpios"); |
| 39 | return regulator_common_of_to_plat(dev, plat, gpios ? "gpios" : "gpio"); |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 40 | } |
| 41 | |
| 42 | static int fixed_regulator_get_value(struct udevice *dev) |
| 43 | { |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 44 | struct dm_regulator_uclass_plat *uc_pdata; |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 45 | |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 46 | uc_pdata = dev_get_uclass_plat(dev); |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 47 | if (!uc_pdata) |
| 48 | return -ENXIO; |
| 49 | |
| 50 | if (uc_pdata->min_uV != uc_pdata->max_uV) { |
| 51 | debug("Invalid constraints for: %s\n", uc_pdata->name); |
| 52 | return -EINVAL; |
| 53 | } |
| 54 | |
| 55 | return uc_pdata->min_uV; |
| 56 | } |
| 57 | |
| 58 | static int fixed_regulator_get_current(struct udevice *dev) |
| 59 | { |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 60 | struct dm_regulator_uclass_plat *uc_pdata; |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 61 | |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 62 | uc_pdata = dev_get_uclass_plat(dev); |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 63 | if (!uc_pdata) |
| 64 | return -ENXIO; |
| 65 | |
| 66 | if (uc_pdata->min_uA != uc_pdata->max_uA) { |
| 67 | debug("Invalid constraints for: %s\n", uc_pdata->name); |
| 68 | return -EINVAL; |
| 69 | } |
| 70 | |
| 71 | return uc_pdata->min_uA; |
| 72 | } |
| 73 | |
Keerthy | 8690d6a | 2017-06-13 09:53:46 +0530 | [diff] [blame] | 74 | static int fixed_regulator_get_enable(struct udevice *dev) |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 75 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 76 | return regulator_common_get_enable(dev, dev_get_plat(dev)); |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | static int fixed_regulator_set_enable(struct udevice *dev, bool enable) |
| 80 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 81 | return regulator_common_set_enable(dev, dev_get_plat(dev), enable); |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 82 | } |
| 83 | |
Philippe Schenker | cdd4bfe | 2022-04-08 10:07:10 +0200 | [diff] [blame] | 84 | static int fixed_clock_regulator_get_enable(struct udevice *dev) |
| 85 | { |
| 86 | struct fixed_clock_regulator_plat *priv = dev_get_priv(dev); |
| 87 | |
| 88 | return priv->clk_enable_counter > 0; |
| 89 | } |
| 90 | |
| 91 | static int fixed_clock_regulator_set_enable(struct udevice *dev, bool enable) |
| 92 | { |
| 93 | struct fixed_clock_regulator_plat *priv = dev_get_priv(dev); |
Eugen Hristev | 81aa192 | 2023-04-19 16:45:25 +0300 | [diff] [blame] | 94 | struct regulator_common_plat *plat = dev_get_plat(dev); |
Philippe Schenker | cdd4bfe | 2022-04-08 10:07:10 +0200 | [diff] [blame] | 95 | int ret = 0; |
| 96 | |
| 97 | if (enable) { |
| 98 | ret = clk_enable(priv->enable_clock); |
| 99 | priv->clk_enable_counter++; |
| 100 | } else { |
| 101 | ret = clk_disable(priv->enable_clock); |
| 102 | priv->clk_enable_counter--; |
| 103 | } |
| 104 | if (ret) |
| 105 | return ret; |
| 106 | |
Eugen Hristev | 81aa192 | 2023-04-19 16:45:25 +0300 | [diff] [blame] | 107 | if (enable && plat->startup_delay_us) |
| 108 | udelay(plat->startup_delay_us); |
Philippe Schenker | cdd4bfe | 2022-04-08 10:07:10 +0200 | [diff] [blame] | 109 | |
Eugen Hristev | 81aa192 | 2023-04-19 16:45:25 +0300 | [diff] [blame] | 110 | if (!enable && plat->off_on_delay_us) |
| 111 | udelay(plat->off_on_delay_us); |
Philippe Schenker | cdd4bfe | 2022-04-08 10:07:10 +0200 | [diff] [blame] | 112 | |
| 113 | return ret; |
| 114 | } |
| 115 | |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 116 | static const struct dm_regulator_ops fixed_regulator_ops = { |
| 117 | .get_value = fixed_regulator_get_value, |
| 118 | .get_current = fixed_regulator_get_current, |
| 119 | .get_enable = fixed_regulator_get_enable, |
| 120 | .set_enable = fixed_regulator_set_enable, |
| 121 | }; |
| 122 | |
Philippe Schenker | cdd4bfe | 2022-04-08 10:07:10 +0200 | [diff] [blame] | 123 | static const struct dm_regulator_ops fixed_clock_regulator_ops = { |
| 124 | .get_enable = fixed_clock_regulator_get_enable, |
| 125 | .set_enable = fixed_clock_regulator_set_enable, |
| 126 | }; |
| 127 | |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 128 | static const struct udevice_id fixed_regulator_ids[] = { |
| 129 | { .compatible = "regulator-fixed" }, |
| 130 | { }, |
| 131 | }; |
| 132 | |
Philippe Schenker | cdd4bfe | 2022-04-08 10:07:10 +0200 | [diff] [blame] | 133 | static const struct udevice_id fixed_clock_regulator_ids[] = { |
| 134 | { .compatible = "regulator-fixed-clock" }, |
| 135 | { }, |
| 136 | }; |
| 137 | |
Walter Lozano | 2901ac6 | 2020-06-25 01:10:04 -0300 | [diff] [blame] | 138 | U_BOOT_DRIVER(regulator_fixed) = { |
| 139 | .name = "regulator_fixed", |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 140 | .id = UCLASS_REGULATOR, |
| 141 | .ops = &fixed_regulator_ops, |
| 142 | .of_match = fixed_regulator_ids, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 143 | .of_to_plat = fixed_regulator_of_to_plat, |
Philippe Schenker | cdd4bfe | 2022-04-08 10:07:10 +0200 | [diff] [blame] | 144 | .plat_auto = sizeof(struct regulator_common_plat), |
| 145 | }; |
| 146 | |
| 147 | U_BOOT_DRIVER(regulator_fixed_clock) = { |
| 148 | .name = "regulator_fixed_clk", |
| 149 | .id = UCLASS_REGULATOR, |
| 150 | .ops = &fixed_clock_regulator_ops, |
| 151 | .of_match = fixed_clock_regulator_ids, |
| 152 | .of_to_plat = fixed_regulator_of_to_plat, |
| 153 | .plat_auto = sizeof(struct fixed_clock_regulator_plat), |
Przemyslaw Marczak | 3753f28 | 2015-04-20 20:07:48 +0200 | [diff] [blame] | 154 | }; |