blob: 8285f87359e79ea061660ce8e7dec37f4b64aef5 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jim Lin5d309e62012-07-29 20:53:29 +00002/*
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
5 * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
6 * (C) Copyright 2006 DENX Software Engineering
Jim Lin5d309e62012-07-29 20:53:29 +00007 */
8
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060010#include <asm/global_data.h>
Jim Lin5d309e62012-07-29 20:53:29 +000011#include <asm/io.h>
Simon Glass2dd337a2015-09-02 17:24:58 -060012#include <memalign.h>
Jim Lin5d309e62012-07-29 20:53:29 +000013#include <nand.h>
Jim Lin5d309e62012-07-29 20:53:29 +000014#include <asm/arch/clock.h>
15#include <asm/arch/funcmux.h>
Tom Warrenab371962012-09-19 15:50:56 -070016#include <asm/arch-tegra/clk_rst.h>
Simon Glass9bc15642020-02-03 07:36:16 -070017#include <dm/device_compat.h>
Simon Glassc06c1be2020-05-10 11:40:08 -060018#include <linux/bug.h>
Simon Glassdbd79542020-05-10 11:40:11 -060019#include <linux/delay.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090020#include <linux/errno.h>
Tom Rini3bde7e22021-09-22 14:50:35 -040021#include <linux/mtd/rawnand.h>
Tom Warrenab371962012-09-19 15:50:56 -070022#include <asm/gpio.h>
Jim Lin5d309e62012-07-29 20:53:29 +000023#include <fdtdec.h>
Marcel Ziswilerd5c69222015-08-06 00:47:06 +020024#include <bouncebuf.h>
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +020025#include <dm.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060026#include <linux/printk.h>
Jim Lin5d309e62012-07-29 20:53:29 +000027#include "tegra_nand.h"
28
29DECLARE_GLOBAL_DATA_PTR;
30
31#define NAND_CMD_TIMEOUT_MS 10
32
33#define SKIPPED_SPARE_BYTES 4
34
35/* ECC bytes to be generated for tag data */
36#define TAG_ECC_BYTES 4
37
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +020038static const struct udevice_id tegra_nand_dt_ids[] = {
39 {
40 .compatible = "nvidia,tegra20-nand",
41 },
42 { /* sentinel */ }
43};
44
Jim Lin5d309e62012-07-29 20:53:29 +000045/* 64 byte oob block info for large page (== 2KB) device
46 *
47 * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
48 * Skipped bytes(4)
49 * Main area Ecc(36)
50 * Tag data(20)
51 * Tag data Ecc(4)
52 *
53 * Yaffs2 will use 16 tag bytes.
54 */
55static struct nand_ecclayout eccoob = {
56 .eccbytes = 36,
57 .eccpos = {
58 4, 5, 6, 7, 8, 9, 10, 11, 12,
59 13, 14, 15, 16, 17, 18, 19, 20, 21,
60 22, 23, 24, 25, 26, 27, 28, 29, 30,
61 31, 32, 33, 34, 35, 36, 37, 38, 39,
62 },
63 .oobavail = 20,
64 .oobfree = {
65 {
66 .offset = 40,
67 .length = 20,
68 },
69 }
70};
71
72enum {
73 ECC_OK,
74 ECC_TAG_ERROR = 1 << 0,
75 ECC_DATA_ERROR = 1 << 1
76};
77
78/* Timing parameters */
79enum {
80 FDT_NAND_MAX_TRP_TREA,
81 FDT_NAND_TWB,
82 FDT_NAND_MAX_TCR_TAR_TRR,
83 FDT_NAND_TWHR,
84 FDT_NAND_MAX_TCS_TCH_TALS_TALH,
85 FDT_NAND_TWH,
86 FDT_NAND_TWP,
87 FDT_NAND_TRH,
88 FDT_NAND_TADL,
89
90 FDT_NAND_TIMING_COUNT
91};
92
93/* Information about an attached NAND chip */
94struct fdt_nand {
95 struct nand_ctlr *reg;
96 int enabled; /* 1 to enable, 0 to disable */
Simon Glass67042a22015-01-05 20:05:36 -070097 struct gpio_desc wp_gpio; /* write-protect GPIO */
Jim Lin5d309e62012-07-29 20:53:29 +000098 s32 width; /* bit width, normally 8 */
99 u32 timing[FDT_NAND_TIMING_COUNT];
100};
101
102struct nand_drv {
103 struct nand_ctlr *reg;
Jim Lin5d309e62012-07-29 20:53:29 +0000104 struct fdt_nand config;
105};
106
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200107struct tegra_nand_info {
108 struct udevice *dev;
109 struct nand_drv nand_ctrl;
110 struct nand_chip nand_chip;
111};
Jim Lin5d309e62012-07-29 20:53:29 +0000112
Jim Lin5d309e62012-07-29 20:53:29 +0000113/**
114 * Wait for command completion
115 *
116 * @param reg nand_ctlr structure
117 * @return
118 * 1 - Command completed
119 * 0 - Timeout
120 */
121static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
122{
123 u32 reg_val;
124 int running;
125 int i;
126
127 for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
128 if ((readl(&reg->command) & CMD_GO) ||
129 !(readl(&reg->status) & STATUS_RBSY0) ||
130 !(readl(&reg->isr) & ISR_IS_CMD_DONE)) {
131 udelay(1);
132 continue;
133 }
134 reg_val = readl(&reg->dma_mst_ctrl);
135 /*
136 * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
137 * is set, that means DMA engine is running.
138 *
139 * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
140 * is cleared, indicating DMA transfer completion.
141 */
142 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
143 DMA_MST_CTRL_EN_B_ENABLE);
144 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
145 return 1;
146 udelay(1);
147 }
148 return 0;
149}
150
151/**
152 * Read one byte from the chip
153 *
154 * @param mtd MTD device structure
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100155 * Return: data byte
Jim Lin5d309e62012-07-29 20:53:29 +0000156 *
157 * Read function for 8bit bus-width
158 */
159static uint8_t read_byte(struct mtd_info *mtd)
160{
Scott Wood17fed142016-05-30 13:57:56 -0500161 struct nand_chip *chip = mtd_to_nand(mtd);
Jim Lin5d309e62012-07-29 20:53:29 +0000162 struct nand_drv *info;
163
Scott Wood17fed142016-05-30 13:57:56 -0500164 info = (struct nand_drv *)nand_get_controller_data(chip);
Jim Lin5d309e62012-07-29 20:53:29 +0000165
Marcel Ziswilerdf13b142015-08-06 00:47:05 +0200166 writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
167 &info->reg->command);
168 if (!nand_waitfor_cmd_completion(info->reg))
169 printf("Command timeout\n");
Jim Lin5d309e62012-07-29 20:53:29 +0000170
Marcel Ziswilerdf13b142015-08-06 00:47:05 +0200171 return (uint8_t)readl(&info->reg->resp);
Jim Lin5d309e62012-07-29 20:53:29 +0000172}
173
174/**
Lucas Stach8a538552012-10-07 11:29:38 +0000175 * Read len bytes from the chip into a buffer
176 *
177 * @param mtd MTD device structure
178 * @param buf buffer to store data to
179 * @param len number of bytes to read
180 *
181 * Read function for 8bit bus-width
182 */
183static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
184{
185 int i, s;
186 unsigned int reg;
Scott Wood17fed142016-05-30 13:57:56 -0500187 struct nand_chip *chip = mtd_to_nand(mtd);
188 struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip);
Lucas Stach8a538552012-10-07 11:29:38 +0000189
190 for (i = 0; i < len; i += 4) {
191 s = (len - i) > 4 ? 4 : len - i;
192 writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
193 ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
194 &info->reg->command);
195 if (!nand_waitfor_cmd_completion(info->reg))
196 puts("Command timeout during read_buf\n");
197 reg = readl(&info->reg->resp);
198 memcpy(buf + i, &reg, s);
199 }
200}
201
202/**
Jim Lin5d309e62012-07-29 20:53:29 +0000203 * Check NAND status to see if it is ready or not
204 *
205 * @param mtd MTD device structure
206 * @return
207 * 1 - ready
208 * 0 - not ready
209 */
210static int nand_dev_ready(struct mtd_info *mtd)
211{
Scott Wood17fed142016-05-30 13:57:56 -0500212 struct nand_chip *chip = mtd_to_nand(mtd);
Jim Lin5d309e62012-07-29 20:53:29 +0000213 int reg_val;
214 struct nand_drv *info;
215
Scott Wood17fed142016-05-30 13:57:56 -0500216 info = (struct nand_drv *)nand_get_controller_data(chip);
Jim Lin5d309e62012-07-29 20:53:29 +0000217
218 reg_val = readl(&info->reg->status);
219 if (reg_val & STATUS_RBSY0)
220 return 1;
221 else
222 return 0;
223}
224
225/* Dummy implementation: we don't support multiple chips */
226static void nand_select_chip(struct mtd_info *mtd, int chipnr)
227{
228 switch (chipnr) {
229 case -1:
230 case 0:
231 break;
232
233 default:
234 BUG();
235 }
236}
237
238/**
239 * Clear all interrupt status bits
240 *
241 * @param reg nand_ctlr structure
242 */
243static void nand_clear_interrupt_status(struct nand_ctlr *reg)
244{
245 u32 reg_val;
246
247 /* Clear interrupt status */
248 reg_val = readl(&reg->isr);
249 writel(reg_val, &reg->isr);
250}
251
252/**
253 * Send command to NAND device
254 *
255 * @param mtd MTD device structure
256 * @param command the command to be sent
257 * @param column the column address for this command, -1 if none
258 * @param page_addr the page address for this command, -1 if none
259 */
260static void nand_command(struct mtd_info *mtd, unsigned int command,
261 int column, int page_addr)
262{
Scott Wood17fed142016-05-30 13:57:56 -0500263 struct nand_chip *chip = mtd_to_nand(mtd);
Jim Lin5d309e62012-07-29 20:53:29 +0000264 struct nand_drv *info;
265
Scott Wood17fed142016-05-30 13:57:56 -0500266 info = (struct nand_drv *)nand_get_controller_data(chip);
Jim Lin5d309e62012-07-29 20:53:29 +0000267
268 /*
269 * Write out the command to the device.
270 *
271 * Only command NAND_CMD_RESET or NAND_CMD_READID will come
272 * here before mtd->writesize is initialized.
273 */
274
275 /* Emulate NAND_CMD_READOOB */
276 if (command == NAND_CMD_READOOB) {
277 assert(mtd->writesize != 0);
278 column += mtd->writesize;
279 command = NAND_CMD_READ0;
280 }
281
282 /* Adjust columns for 16 bit bus-width */
283 if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
284 column >>= 1;
285
286 nand_clear_interrupt_status(info->reg);
287
288 /* Stop DMA engine, clear DMA completion status */
289 writel(DMA_MST_CTRL_EN_A_DISABLE
290 | DMA_MST_CTRL_EN_B_DISABLE
291 | DMA_MST_CTRL_IS_DMA_DONE,
292 &info->reg->dma_mst_ctrl);
293
294 /*
295 * Program and erase have their own busy handlers
296 * status and sequential in needs no delay
297 */
298 switch (command) {
299 case NAND_CMD_READID:
300 writel(NAND_CMD_READID, &info->reg->cmd_reg1);
Lucas Stach8a538552012-10-07 11:29:38 +0000301 writel(column & 0xFF, &info->reg->addr_reg1);
Marcel Ziswilerdf13b142015-08-06 00:47:05 +0200302 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
303 &info->reg->command);
Jim Lin5d309e62012-07-29 20:53:29 +0000304 break;
Lucas Stach8a538552012-10-07 11:29:38 +0000305 case NAND_CMD_PARAM:
306 writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
307 writel(column & 0xFF, &info->reg->addr_reg1);
308 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
309 &info->reg->command);
310 break;
Jim Lin5d309e62012-07-29 20:53:29 +0000311 case NAND_CMD_READ0:
312 writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
313 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
314 writel((page_addr << 16) | (column & 0xFFFF),
315 &info->reg->addr_reg1);
316 writel(page_addr >> 16, &info->reg->addr_reg2);
317 return;
318 case NAND_CMD_SEQIN:
319 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
320 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
321 writel((page_addr << 16) | (column & 0xFFFF),
322 &info->reg->addr_reg1);
323 writel(page_addr >> 16,
324 &info->reg->addr_reg2);
325 return;
326 case NAND_CMD_PAGEPROG:
327 return;
328 case NAND_CMD_ERASE1:
329 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
330 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
331 writel(page_addr, &info->reg->addr_reg1);
332 writel(CMD_GO | CMD_CLE | CMD_ALE |
333 CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
334 &info->reg->command);
335 break;
336 case NAND_CMD_ERASE2:
337 return;
338 case NAND_CMD_STATUS:
339 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
340 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
341 | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
342 | CMD_CE0,
343 &info->reg->command);
Jim Lin5d309e62012-07-29 20:53:29 +0000344 break;
345 case NAND_CMD_RESET:
346 writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
347 writel(CMD_GO | CMD_CLE | CMD_CE0,
348 &info->reg->command);
349 break;
350 case NAND_CMD_RNDOUT:
351 default:
352 printf("%s: Unsupported command %d\n", __func__, command);
353 return;
354 }
355 if (!nand_waitfor_cmd_completion(info->reg))
356 printf("Command 0x%02X timeout\n", command);
357}
358
359/**
360 * Check whether the pointed buffer are all 0xff (blank).
361 *
362 * @param buf data buffer for blank check
363 * @param len length of the buffer in byte
364 * @return
365 * 1 - blank
366 * 0 - non-blank
367 */
368static int blank_check(u8 *buf, int len)
369{
370 int i;
371
372 for (i = 0; i < len; i++)
373 if (buf[i] != 0xFF)
374 return 0;
375 return 1;
376}
377
378/**
379 * After a DMA transfer for read, we call this function to see whether there
380 * is any uncorrectable error on the pointed data buffer or oob buffer.
381 *
382 * @param reg nand_ctlr structure
383 * @param databuf data buffer
384 * @param a_len data buffer length
385 * @param oobbuf oob buffer
386 * @param b_len oob buffer length
387 * @return
388 * ECC_OK - no ECC error or correctable ECC error
389 * ECC_TAG_ERROR - uncorrectable tag ECC error
390 * ECC_DATA_ERROR - uncorrectable data ECC error
391 * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
392 */
393static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
394 int a_len, u8 *oobbuf, int b_len)
395{
396 int return_val = ECC_OK;
397 u32 reg_val;
398
399 if (!(readl(&reg->isr) & ISR_IS_ECC_ERR))
400 return ECC_OK;
401
402 /*
403 * Area A is used for the data block (databuf). Area B is used for
404 * the spare block (oobbuf)
405 */
406 reg_val = readl(&reg->dec_status);
407 if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
408 reg_val = readl(&reg->bch_dec_status_buf);
409 /*
410 * If uncorrectable error occurs on data area, then see whether
411 * they are all FF. If all are FF, it's a blank page.
412 * Not error.
413 */
414 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
415 !blank_check(databuf, a_len))
416 return_val |= ECC_DATA_ERROR;
417 }
418
419 if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
420 reg_val = readl(&reg->bch_dec_status_buf);
421 /*
422 * If uncorrectable error occurs on tag area, then see whether
423 * they are all FF. If all are FF, it's a blank page.
424 * Not error.
425 */
426 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
427 !blank_check(oobbuf, b_len))
428 return_val |= ECC_TAG_ERROR;
429 }
430
431 return return_val;
432}
433
434/**
435 * Set GO bit to send command to device
436 *
437 * @param reg nand_ctlr structure
438 */
439static void start_command(struct nand_ctlr *reg)
440{
441 u32 reg_val;
442
443 reg_val = readl(&reg->command);
444 reg_val |= CMD_GO;
445 writel(reg_val, &reg->command);
446}
447
448/**
449 * Clear command GO bit, DMA GO bit, and DMA completion status
450 *
451 * @param reg nand_ctlr structure
452 */
453static void stop_command(struct nand_ctlr *reg)
454{
455 /* Stop command */
456 writel(0, &reg->command);
457
458 /* Stop DMA engine and clear DMA completion status */
459 writel(DMA_MST_CTRL_GO_DISABLE
460 | DMA_MST_CTRL_IS_DMA_DONE,
461 &reg->dma_mst_ctrl);
462}
463
464/**
465 * Set up NAND bus width and page size
466 *
467 * @param info nand_info structure
468 * @param *reg_val address of reg_val
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100469 * Return: 0 if ok, -1 on error
Jim Lin5d309e62012-07-29 20:53:29 +0000470 */
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200471static int set_bus_width_page_size(struct mtd_info *our_mtd,
472 struct fdt_nand *config, u32 *reg_val)
Jim Lin5d309e62012-07-29 20:53:29 +0000473{
474 if (config->width == 8)
475 *reg_val = CFG_BUS_WIDTH_8BIT;
476 else if (config->width == 16)
477 *reg_val = CFG_BUS_WIDTH_16BIT;
478 else {
479 debug("%s: Unsupported bus width %d\n", __func__,
480 config->width);
481 return -1;
482 }
483
484 if (our_mtd->writesize == 512)
485 *reg_val |= CFG_PAGE_SIZE_512;
486 else if (our_mtd->writesize == 2048)
487 *reg_val |= CFG_PAGE_SIZE_2048;
488 else if (our_mtd->writesize == 4096)
489 *reg_val |= CFG_PAGE_SIZE_4096;
490 else {
491 debug("%s: Unsupported page size %d\n", __func__,
492 our_mtd->writesize);
493 return -1;
494 }
495
496 return 0;
497}
498
499/**
500 * Page read/write function
501 *
502 * @param mtd mtd info structure
503 * @param chip nand chip info structure
504 * @param buf data buffer
505 * @param page page number
506 * @param with_ecc 1 to enable ECC, 0 to disable ECC
507 * @param is_writing 0 for read, 1 for write
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100508 * Return: 0 when successfully completed
Jim Lin5d309e62012-07-29 20:53:29 +0000509 * -EIO when command timeout
510 */
511static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
512 uint8_t *buf, int page, int with_ecc, int is_writing)
513{
514 u32 reg_val;
515 int tag_size;
516 struct nand_oobfree *free = chip->ecc.layout->oobfree;
517 /* 4*128=512 (byte) is the value that our HW can support. */
518 ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
519 char *tag_ptr;
520 struct nand_drv *info;
521 struct fdt_nand *config;
Marcel Ziswilerd5c69222015-08-06 00:47:06 +0200522 unsigned int bbflags;
523 struct bounce_buffer bbstate, bbstate_oob;
Jim Lin5d309e62012-07-29 20:53:29 +0000524
525 if ((uintptr_t)buf & 0x03) {
526 printf("buf %p has to be 4-byte aligned\n", buf);
527 return -EINVAL;
528 }
529
Scott Wood17fed142016-05-30 13:57:56 -0500530 info = (struct nand_drv *)nand_get_controller_data(chip);
Jim Lin5d309e62012-07-29 20:53:29 +0000531 config = &info->config;
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200532 if (set_bus_width_page_size(mtd, config, &reg_val))
Jim Lin5d309e62012-07-29 20:53:29 +0000533 return -EINVAL;
534
535 /* Need to be 4-byte aligned */
536 tag_ptr = (char *)tag_buf;
537
538 stop_command(info->reg);
539
Marcel Ziswilerd5c69222015-08-06 00:47:06 +0200540 if (is_writing)
541 bbflags = GEN_BB_READ;
542 else
543 bbflags = GEN_BB_WRITE;
544
545 bounce_buffer_start(&bbstate, (void *)buf, 1 << chip->page_shift,
546 bbflags);
Jim Lin5d309e62012-07-29 20:53:29 +0000547 writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
Marcel Ziswilerd5c69222015-08-06 00:47:06 +0200548 writel(virt_to_phys(bbstate.bounce_buffer), &info->reg->data_block_ptr);
Jim Lin5d309e62012-07-29 20:53:29 +0000549
Marcel Ziswilerd5c69222015-08-06 00:47:06 +0200550 /* Set ECC selection, configure ECC settings */
Jim Lin5d309e62012-07-29 20:53:29 +0000551 if (with_ecc) {
Jim Lin5d309e62012-07-29 20:53:29 +0000552 if (is_writing)
553 memcpy(tag_ptr, chip->oob_poi + free->offset,
Marcel Ziswilerd5c69222015-08-06 00:47:06 +0200554 chip->ecc.layout->oobavail + TAG_ECC_BYTES);
Jim Lin5d309e62012-07-29 20:53:29 +0000555 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
556 reg_val |= (CFG_SKIP_SPARE_SEL_4
557 | CFG_SKIP_SPARE_ENABLE
558 | CFG_HW_ECC_CORRECTION_ENABLE
559 | CFG_ECC_EN_TAG_DISABLE
560 | CFG_HW_ECC_SEL_RS
561 | CFG_HW_ECC_ENABLE
562 | CFG_TVAL4
563 | (tag_size - 1));
564
565 if (!is_writing)
566 tag_size += SKIPPED_SPARE_BYTES;
Marcel Ziswilerd5c69222015-08-06 00:47:06 +0200567 bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size,
568 bbflags);
Jim Lin5d309e62012-07-29 20:53:29 +0000569 } else {
570 tag_size = mtd->oobsize;
571 reg_val |= (CFG_SKIP_SPARE_DISABLE
572 | CFG_HW_ECC_CORRECTION_DISABLE
573 | CFG_ECC_EN_TAG_DISABLE
574 | CFG_HW_ECC_DISABLE
575 | (tag_size - 1));
Marcel Ziswilerd5c69222015-08-06 00:47:06 +0200576 bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi,
577 tag_size, bbflags);
Jim Lin5d309e62012-07-29 20:53:29 +0000578 }
579 writel(reg_val, &info->reg->config);
Marcel Ziswilerd5c69222015-08-06 00:47:06 +0200580 writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
Jim Lin5d309e62012-07-29 20:53:29 +0000581 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
Jim Lin5d309e62012-07-29 20:53:29 +0000582 writel(tag_size - 1, &info->reg->dma_cfg_b);
583
584 nand_clear_interrupt_status(info->reg);
585
586 reg_val = CMD_CLE | CMD_ALE
587 | CMD_SEC_CMD
588 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
589 | CMD_A_VALID
590 | CMD_B_VALID
591 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
592 | CMD_CE0;
593 if (!is_writing)
594 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
595 else
596 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
597 writel(reg_val, &info->reg->command);
598
599 /* Setup DMA engine */
600 reg_val = DMA_MST_CTRL_GO_ENABLE
601 | DMA_MST_CTRL_BURST_8WORDS
602 | DMA_MST_CTRL_EN_A_ENABLE
603 | DMA_MST_CTRL_EN_B_ENABLE;
604
605 if (!is_writing)
606 reg_val |= DMA_MST_CTRL_DIR_READ;
607 else
608 reg_val |= DMA_MST_CTRL_DIR_WRITE;
609
610 writel(reg_val, &info->reg->dma_mst_ctrl);
611
612 start_command(info->reg);
613
614 if (!nand_waitfor_cmd_completion(info->reg)) {
615 if (!is_writing)
616 printf("Read Page 0x%X timeout ", page);
617 else
618 printf("Write Page 0x%X timeout ", page);
619 if (with_ecc)
620 printf("with ECC");
621 else
622 printf("without ECC");
623 printf("\n");
624 return -EIO;
625 }
626
Marcel Ziswilerd5c69222015-08-06 00:47:06 +0200627 bounce_buffer_stop(&bbstate_oob);
628 bounce_buffer_stop(&bbstate);
629
Jim Lin5d309e62012-07-29 20:53:29 +0000630 if (with_ecc && !is_writing) {
631 memcpy(chip->oob_poi, tag_ptr,
632 SKIPPED_SPARE_BYTES);
633 memcpy(chip->oob_poi + free->offset,
634 tag_ptr + SKIPPED_SPARE_BYTES,
635 chip->ecc.layout->oobavail);
636 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
637 1 << chip->page_shift,
638 (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
639 chip->ecc.layout->oobavail);
640 if (reg_val & ECC_TAG_ERROR)
641 printf("Read Page 0x%X tag ECC error\n", page);
642 if (reg_val & ECC_DATA_ERROR)
643 printf("Read Page 0x%X data ECC error\n",
644 page);
645 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
646 return -EIO;
647 }
648 return 0;
649}
650
651/**
652 * Hardware ecc based page read function
653 *
654 * @param mtd mtd info structure
655 * @param chip nand chip info structure
656 * @param buf buffer to store read data
657 * @param page page number to read
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100658 * Return: 0 when successfully completed
Jim Lin5d309e62012-07-29 20:53:29 +0000659 * -EIO when command timeout
660 */
661static int nand_read_page_hwecc(struct mtd_info *mtd,
Sergey Lapin3a38a552013-01-14 03:46:50 +0000662 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
Jim Lin5d309e62012-07-29 20:53:29 +0000663{
664 return nand_rw_page(mtd, chip, buf, page, 1, 0);
665}
666
667/**
668 * Hardware ecc based page write function
669 *
670 * @param mtd mtd info structure
671 * @param chip nand chip info structure
672 * @param buf data buffer
673 */
Sergey Lapin3a38a552013-01-14 03:46:50 +0000674static int nand_write_page_hwecc(struct mtd_info *mtd,
Scott Wood46e13102016-05-30 13:57:57 -0500675 struct nand_chip *chip, const uint8_t *buf, int oob_required,
676 int page)
Jim Lin5d309e62012-07-29 20:53:29 +0000677{
Jim Lin5d309e62012-07-29 20:53:29 +0000678 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
Sergey Lapin3a38a552013-01-14 03:46:50 +0000679 return 0;
Jim Lin5d309e62012-07-29 20:53:29 +0000680}
681
682
683/**
684 * Read raw page data without ecc
685 *
686 * @param mtd mtd info structure
687 * @param chip nand chip info structure
688 * @param buf buffer to store read data
689 * @param page page number to read
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100690 * Return: 0 when successfully completed
Jim Lin5d309e62012-07-29 20:53:29 +0000691 * -EINVAL when chip->oob_poi is not double-word aligned
692 * -EIO when command timeout
693 */
694static int nand_read_page_raw(struct mtd_info *mtd,
Sergey Lapin3a38a552013-01-14 03:46:50 +0000695 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
Jim Lin5d309e62012-07-29 20:53:29 +0000696{
697 return nand_rw_page(mtd, chip, buf, page, 0, 0);
698}
699
700/**
701 * Raw page write function
702 *
703 * @param mtd mtd info structure
704 * @param chip nand chip info structure
705 * @param buf data buffer
706 */
Sergey Lapin3a38a552013-01-14 03:46:50 +0000707static int nand_write_page_raw(struct mtd_info *mtd,
Scott Wood46e13102016-05-30 13:57:57 -0500708 struct nand_chip *chip, const uint8_t *buf,
709 int oob_required, int page)
Jim Lin5d309e62012-07-29 20:53:29 +0000710{
Jim Lin5d309e62012-07-29 20:53:29 +0000711 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
Sergey Lapin3a38a552013-01-14 03:46:50 +0000712 return 0;
Jim Lin5d309e62012-07-29 20:53:29 +0000713}
714
715/**
716 * OOB data read/write function
717 *
718 * @param mtd mtd info structure
719 * @param chip nand chip info structure
720 * @param page page number to read
721 * @param with_ecc 1 to enable ECC, 0 to disable ECC
722 * @param is_writing 0 for read, 1 for write
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100723 * Return: 0 when successfully completed
Jim Lin5d309e62012-07-29 20:53:29 +0000724 * -EINVAL when chip->oob_poi is not double-word aligned
725 * -EIO when command timeout
726 */
727static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
728 int page, int with_ecc, int is_writing)
729{
730 u32 reg_val;
731 int tag_size;
732 struct nand_oobfree *free = chip->ecc.layout->oobfree;
733 struct nand_drv *info;
Marcel Ziswilerd5c69222015-08-06 00:47:06 +0200734 unsigned int bbflags;
735 struct bounce_buffer bbstate_oob;
Jim Lin5d309e62012-07-29 20:53:29 +0000736
737 if (((int)chip->oob_poi) & 0x03)
738 return -EINVAL;
Scott Wood17fed142016-05-30 13:57:56 -0500739 info = (struct nand_drv *)nand_get_controller_data(chip);
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200740 if (set_bus_width_page_size(mtd, &info->config, &reg_val))
Jim Lin5d309e62012-07-29 20:53:29 +0000741 return -EINVAL;
742
743 stop_command(info->reg);
744
Jim Lin5d309e62012-07-29 20:53:29 +0000745 /* Set ECC selection */
746 tag_size = mtd->oobsize;
747 if (with_ecc)
748 reg_val |= CFG_ECC_EN_TAG_ENABLE;
749 else
750 reg_val |= (CFG_ECC_EN_TAG_DISABLE);
751
752 reg_val |= ((tag_size - 1) |
753 CFG_SKIP_SPARE_DISABLE |
754 CFG_HW_ECC_CORRECTION_DISABLE |
755 CFG_HW_ECC_DISABLE);
756 writel(reg_val, &info->reg->config);
757
Jim Lin5d309e62012-07-29 20:53:29 +0000758 if (is_writing && with_ecc)
759 tag_size -= TAG_ECC_BYTES;
760
Marcel Ziswilerd5c69222015-08-06 00:47:06 +0200761 if (is_writing)
762 bbflags = GEN_BB_READ;
763 else
764 bbflags = GEN_BB_WRITE;
765
766 bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, tag_size,
767 bbflags);
768 writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
769
770 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
771
Jim Lin5d309e62012-07-29 20:53:29 +0000772 writel(tag_size - 1, &info->reg->dma_cfg_b);
773
774 nand_clear_interrupt_status(info->reg);
775
776 reg_val = CMD_CLE | CMD_ALE
777 | CMD_SEC_CMD
778 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
779 | CMD_B_VALID
780 | CMD_CE0;
781 if (!is_writing)
782 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
783 else
784 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
785 writel(reg_val, &info->reg->command);
786
787 /* Setup DMA engine */
788 reg_val = DMA_MST_CTRL_GO_ENABLE
789 | DMA_MST_CTRL_BURST_8WORDS
790 | DMA_MST_CTRL_EN_B_ENABLE;
791 if (!is_writing)
792 reg_val |= DMA_MST_CTRL_DIR_READ;
793 else
794 reg_val |= DMA_MST_CTRL_DIR_WRITE;
795
796 writel(reg_val, &info->reg->dma_mst_ctrl);
797
798 start_command(info->reg);
799
800 if (!nand_waitfor_cmd_completion(info->reg)) {
801 if (!is_writing)
802 printf("Read OOB of Page 0x%X timeout\n", page);
803 else
804 printf("Write OOB of Page 0x%X timeout\n", page);
805 return -EIO;
806 }
807
Marcel Ziswilerd5c69222015-08-06 00:47:06 +0200808 bounce_buffer_stop(&bbstate_oob);
809
Jim Lin5d309e62012-07-29 20:53:29 +0000810 if (with_ecc && !is_writing) {
811 reg_val = (u32)check_ecc_error(info->reg, 0, 0,
812 (u8 *)(chip->oob_poi + free->offset),
813 chip->ecc.layout->oobavail);
814 if (reg_val & ECC_TAG_ERROR)
815 printf("Read OOB of Page 0x%X tag ECC error\n", page);
816 }
817 return 0;
818}
819
820/**
821 * OOB data read function
822 *
823 * @param mtd mtd info structure
824 * @param chip nand chip info structure
825 * @param page page number to read
Jim Lin5d309e62012-07-29 20:53:29 +0000826 */
827static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
Sergey Lapin3a38a552013-01-14 03:46:50 +0000828 int page)
Jim Lin5d309e62012-07-29 20:53:29 +0000829{
Sergey Lapin3a38a552013-01-14 03:46:50 +0000830 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
Jim Lin5d309e62012-07-29 20:53:29 +0000831 nand_rw_oob(mtd, chip, page, 0, 0);
Sergey Lapin3a38a552013-01-14 03:46:50 +0000832 return 0;
Jim Lin5d309e62012-07-29 20:53:29 +0000833}
834
835/**
836 * OOB data write function
837 *
838 * @param mtd mtd info structure
839 * @param chip nand chip info structure
840 * @param page page number to write
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100841 * Return: 0 when successfully completed
Jim Lin5d309e62012-07-29 20:53:29 +0000842 * -EINVAL when chip->oob_poi is not double-word aligned
843 * -EIO when command timeout
844 */
845static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
846 int page)
847{
848 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
849
850 return nand_rw_oob(mtd, chip, page, 0, 1);
851}
852
853/**
854 * Set up NAND memory timings according to the provided parameters
855 *
856 * @param timing Timing parameters
857 * @param reg NAND controller register address
858 */
859static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
860 struct nand_ctlr *reg)
861{
862 u32 reg_val, clk_rate, clk_period, time_val;
863
864 clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
865 CLOCK_ID_PERIPH) / 1000000;
866 clk_period = 1000 / clk_rate;
867 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
868 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
869 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
870 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
871 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
872 if (time_val > 2)
873 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
874 TIMING_TCR_TAR_TRR_CNT_MASK;
875 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
876 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
877 time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
878 if (time_val > 1)
879 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
880 TIMING_TCS_CNT_MASK;
881 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
882 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
883 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
884 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
885 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
886 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
887 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
888 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
889 writel(reg_val, &reg->timing);
890
891 reg_val = 0;
892 time_val = timing[FDT_NAND_TADL] / clk_period;
893 if (time_val > 2)
894 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
895 writel(reg_val, &reg->timing2);
896}
897
898/**
899 * Decode NAND parameters from the device tree
900 *
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200901 * @param dev Driver model device
902 * @param config Device tree NAND configuration
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100903 * Return: 0 if ok, -ve on error (FDT_ERR_...)
Jim Lin5d309e62012-07-29 20:53:29 +0000904 */
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200905static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config)
Jim Lin5d309e62012-07-29 20:53:29 +0000906{
907 int err;
908
Johan Jonker8d5d8e02023-03-13 01:32:04 +0100909 config->reg = dev_read_addr_ptr(dev);
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200910 config->enabled = dev_read_enabled(dev);
911 config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8);
912 err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio,
913 GPIOD_IS_OUT);
Jim Lin5d309e62012-07-29 20:53:29 +0000914 if (err)
915 return err;
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200916 err = dev_read_u32_array(dev, "nvidia,timing", config->timing,
917 FDT_NAND_TIMING_COUNT);
Jim Lin5d309e62012-07-29 20:53:29 +0000918 if (err < 0)
919 return err;
920
Jim Lin5d309e62012-07-29 20:53:29 +0000921 return 0;
922}
923
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200924static int tegra_probe(struct udevice *dev)
Jim Lin5d309e62012-07-29 20:53:29 +0000925{
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200926 struct tegra_nand_info *tegra = dev_get_priv(dev);
927 struct nand_chip *nand = &tegra->nand_chip;
928 struct nand_drv *info = &tegra->nand_ctrl;
Jim Lin5d309e62012-07-29 20:53:29 +0000929 struct fdt_nand *config = &info->config;
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200930 struct mtd_info *our_mtd;
931 int ret;
Jim Lin5d309e62012-07-29 20:53:29 +0000932
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200933 if (fdt_decode_nand(dev, config)) {
Jim Lin5d309e62012-07-29 20:53:29 +0000934 printf("Could not decode nand-flash in device tree\n");
935 return -1;
936 }
937 if (!config->enabled)
938 return -1;
939 info->reg = config->reg;
940 nand->ecc.mode = NAND_ECC_HW;
941 nand->ecc.layout = &eccoob;
942
943 nand->options = LP_OPTIONS;
944 nand->cmdfunc = nand_command;
945 nand->read_byte = read_byte;
Lucas Stach8a538552012-10-07 11:29:38 +0000946 nand->read_buf = read_buf;
Jim Lin5d309e62012-07-29 20:53:29 +0000947 nand->ecc.read_page = nand_read_page_hwecc;
948 nand->ecc.write_page = nand_write_page_hwecc;
949 nand->ecc.read_page_raw = nand_read_page_raw;
950 nand->ecc.write_page_raw = nand_write_page_raw;
951 nand->ecc.read_oob = nand_read_oob;
952 nand->ecc.write_oob = nand_write_oob;
Sergey Lapin3a38a552013-01-14 03:46:50 +0000953 nand->ecc.strength = 1;
Jim Lin5d309e62012-07-29 20:53:29 +0000954 nand->select_chip = nand_select_chip;
955 nand->dev_ready = nand_dev_ready;
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200956 nand_set_controller_data(nand, &tegra->nand_ctrl);
Jim Lin5d309e62012-07-29 20:53:29 +0000957
Marcel Ziswilercdbf2082015-08-06 00:47:13 +0200958 /* Disable subpage writes as we do not provide ecc->hwctl */
959 nand->options |= NAND_NO_SUBPAGE_WRITE;
960
Jim Lin5d309e62012-07-29 20:53:29 +0000961 /* Adjust controller clock rate */
962 clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
963
964 /* Adjust timing for NAND device */
965 setup_timing(config->timing, info->reg);
966
Simon Glass67042a22015-01-05 20:05:36 -0700967 dm_gpio_set_value(&config->wp_gpio, 1);
Jim Lin5d309e62012-07-29 20:53:29 +0000968
Scott Wood17fed142016-05-30 13:57:56 -0500969 our_mtd = nand_to_mtd(nand);
Jim Lin5d309e62012-07-29 20:53:29 +0000970 ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
971 if (ret)
972 return ret;
973
974 nand->ecc.size = our_mtd->writesize;
975 nand->ecc.bytes = our_mtd->oobsize;
976
977 ret = nand_scan_tail(our_mtd);
978 if (ret)
979 return ret;
980
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200981 ret = nand_register(0, our_mtd);
982 if (ret) {
983 dev_err(dev, "Failed to register MTD: %d\n", ret);
Jim Lin5d309e62012-07-29 20:53:29 +0000984 return ret;
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200985 }
Jim Lin5d309e62012-07-29 20:53:29 +0000986
987 return 0;
988}
989
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200990U_BOOT_DRIVER(tegra_nand) = {
991 .name = "tegra-nand",
992 .id = UCLASS_MTD,
993 .of_match = tegra_nand_dt_ids,
994 .probe = tegra_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700995 .priv_auto = sizeof(struct tegra_nand_info),
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +0200996};
997
Jim Lin5d309e62012-07-29 20:53:29 +0000998void board_nand_init(void)
999{
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +02001000 struct udevice *dev;
1001 int ret;
Jim Lin5d309e62012-07-29 20:53:29 +00001002
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +02001003 ret = uclass_get_device_by_driver(UCLASS_MTD,
Simon Glass65130cd2020-12-28 20:34:56 -07001004 DM_DRIVER_GET(tegra_nand), &dev);
Marcel Ziswilerd6129ec2018-05-07 23:18:41 +02001005 if (ret && ret != -ENODEV)
1006 pr_err("Failed to initialize %s. (error %d)\n", dev->name,
1007 ret);
Jim Lin5d309e62012-07-29 20:53:29 +00001008}