blob: f730e15d04107fd1c9571c9a992f0f8a1e3ec637 [file] [log] [blame]
Yifeng Zhao9e9021e2021-06-07 16:40:29 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Rockchip NAND Flash controller driver.
4 * Copyright (C) 2021 Rockchip Inc.
5 * Author: Yifeng Zhao <yifeng.zhao@rock-chips.com>
6 */
7
Yifeng Zhao9e9021e2021-06-07 16:40:29 +08008#include <asm/io.h>
9#include <clk.h>
10#include <dm.h>
11#include <dm/device_compat.h>
12#include <dm/devres.h>
13#include <fdtdec.h>
14#include <inttypes.h>
15#include <linux/delay.h>
16#include <linux/dma-direction.h>
17#include <linux/dma-mapping.h>
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/mtd/mtd.h>
21#include <linux/mtd/nand.h>
22#include <linux/mtd/partitions.h>
Tom Rini3bde7e22021-09-22 14:50:35 -040023#include <linux/mtd/rawnand.h>
Yifeng Zhao9e9021e2021-06-07 16:40:29 +080024#include <memalign.h>
25#include <nand.h>
26
27/*
28 * NFC Page Data Layout:
29 * 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data +
30 * 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data +
31 * ......
32 * NAND Page Data Layout:
33 * 1024 * n data + m Bytes oob
34 * Original Bad Block Mask Location:
35 * First byte of oob(spare).
36 * nand_chip->oob_poi data layout:
37 * 4Bytes sys data + .... + 4Bytes sys data + ECC data.
38 */
39
40/* NAND controller register definition */
41#define NFC_READ (0)
42#define NFC_WRITE (1)
43
44#define NFC_FMCTL (0x00)
45#define FMCTL_CE_SEL_M 0xFF
46#define FMCTL_CE_SEL(x) (1 << (x))
47#define FMCTL_WP BIT(8)
48#define FMCTL_RDY BIT(9)
49
50#define NFC_FMWAIT (0x04)
51#define FLCTL_RST BIT(0)
52#define FLCTL_WR (1) /* 0: read, 1: write */
53#define FLCTL_XFER_ST BIT(2)
54#define FLCTL_XFER_EN BIT(3)
55#define FLCTL_ACORRECT BIT(10) /* Auto correct error bits. */
56#define FLCTL_XFER_READY BIT(20)
57#define FLCTL_XFER_SECTOR (22)
58#define FLCTL_TOG_FIX BIT(29)
59
60#define BCHCTL_BANK_M (7 << 5)
61#define BCHCTL_BANK (5)
62
63#define DMA_ST BIT(0)
64#define DMA_WR (1) /* 0: write, 1: read */
65#define DMA_EN BIT(2)
66#define DMA_AHB_SIZE (3) /* 0: 1, 1: 2, 2: 4 */
67#define DMA_BURST_SIZE (6) /* 0: 1, 3: 4, 5: 8, 7: 16 */
68#define DMA_INC_NUM (9) /* 1 - 16 */
69
70#define ECC_ERR_CNT(x, e) ((((x) >> (e).low) & (e).low_mask) |\
71 (((x) >> (e).high) & (e).high_mask) << (e).low_bn)
72#define INT_DMA BIT(0)
73#define NFC_BANK (0x800)
74#define NFC_BANK_STEP (0x100)
75#define BANK_DATA (0x00)
76#define BANK_ADDR (0x04)
77#define BANK_CMD (0x08)
78#define NFC_SRAM0 (0x1000)
79#define NFC_SRAM1 (0x1400)
80#define NFC_SRAM_SIZE (0x400)
81#define NFC_TIMEOUT_MS (500)
82#define NFC_MAX_OOB_PER_STEP 128
83#define NFC_MIN_OOB_PER_STEP 64
84#define MAX_DATA_SIZE 0xFFFC
85#define MAX_ADDRESS_CYC 6
86#define NFC_ECC_MAX_MODES 4
87#define NFC_RB_DELAY_US 50
88#define NFC_MAX_PAGE_SIZE (16 * 1024)
89#define NFC_MAX_OOB_SIZE (16 * 128)
90#define NFC_MAX_NSELS (8) /* Some Socs only have 1 or 2 CSs. */
91#define NFC_SYS_DATA_SIZE (4) /* 4 bytes sys data in oob pre 1024 data.*/
92#define RK_DEFAULT_CLOCK_RATE (150 * 1000 * 1000) /* 150 Mhz */
93#define ACCTIMING(csrw, rwpw, rwcs) ((csrw) << 12 | (rwpw) << 5 | (rwcs))
94
95enum nfc_type {
96 NFC_V6,
97 NFC_V8,
98 NFC_V9,
99};
100
101/**
102 * struct rk_ecc_cnt_status: represent a ecc status data.
103 * @err_flag_bit: error flag bit index at register.
104 * @low: ECC count low bit index at register.
105 * @low_mask: mask bit.
106 * @low_bn: ECC count low bit number.
107 * @high: ECC count high bit index at register.
108 * @high_mask: mask bit
109 */
110struct ecc_cnt_status {
111 u8 err_flag_bit;
112 u8 low;
113 u8 low_mask;
114 u8 low_bn;
115 u8 high;
116 u8 high_mask;
117};
118
119/**
120 * @type: NFC version
121 * @ecc_strengths: ECC strengths
122 * @ecc_cfgs: ECC config values
123 * @flctl_off: FLCTL register offset
124 * @bchctl_off: BCHCTL register offset
125 * @dma_data_buf_off: DMA_DATA_BUF register offset
126 * @dma_oob_buf_off: DMA_OOB_BUF register offset
127 * @dma_cfg_off: DMA_CFG register offset
128 * @dma_st_off: DMA_ST register offset
129 * @bch_st_off: BCG_ST register offset
130 * @randmz_off: RANDMZ register offset
131 * @int_en_off: interrupt enable register offset
132 * @int_clr_off: interrupt clean register offset
133 * @int_st_off: interrupt status register offset
134 * @oob0_off: oob0 register offset
135 * @oob1_off: oob1 register offset
136 * @ecc0: represent ECC0 status data
137 * @ecc1: represent ECC1 status data
138 */
139struct nfc_cfg {
140 enum nfc_type type;
141 u8 ecc_strengths[NFC_ECC_MAX_MODES];
142 u32 ecc_cfgs[NFC_ECC_MAX_MODES];
143 u32 flctl_off;
144 u32 bchctl_off;
145 u32 dma_cfg_off;
146 u32 dma_data_buf_off;
147 u32 dma_oob_buf_off;
148 u32 dma_st_off;
149 u32 bch_st_off;
150 u32 randmz_off;
151 u32 int_en_off;
152 u32 int_clr_off;
153 u32 int_st_off;
154 u32 oob0_off;
155 u32 oob1_off;
156 struct ecc_cnt_status ecc0;
157 struct ecc_cnt_status ecc1;
158};
159
160struct rk_nfc_nand_chip {
161 struct nand_chip chip;
162
163 u16 boot_blks;
164 u16 metadata_size;
165 u32 boot_ecc;
166 u32 timing;
167
168 u8 nsels;
169 u8 sels[0];
170 /* Nothing after this field. */
171};
172
173struct rk_nfc {
174 struct nand_hw_control controller;
175 const struct nfc_cfg *cfg;
176 struct udevice *dev;
177
178 struct clk *nfc_clk;
179 struct clk *ahb_clk;
180 void __iomem *regs;
181
182 int selected_bank;
183 u32 band_offset;
184 u32 cur_ecc;
185 u32 cur_timing;
186
187 u8 *page_buf;
188 u32 *oob_buf;
189
190 unsigned long assigned_cs;
191};
192
193static inline struct rk_nfc_nand_chip *rk_nfc_to_rknand(struct nand_chip *chip)
194{
195 return container_of(chip, struct rk_nfc_nand_chip, chip);
196}
197
198static inline u8 *rk_nfc_buf_to_data_ptr(struct nand_chip *chip, const u8 *p, int i)
199{
200 return (u8 *)p + i * chip->ecc.size;
201}
202
203static inline u8 *rk_nfc_buf_to_oob_ptr(struct nand_chip *chip, int i)
204{
205 u8 *poi;
206
207 poi = chip->oob_poi + i * NFC_SYS_DATA_SIZE;
208
209 return poi;
210}
211
212static inline u8 *rk_nfc_buf_to_oob_ecc_ptr(struct nand_chip *chip, int i)
213{
214 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
215 u8 *poi;
216
217 poi = chip->oob_poi + rknand->metadata_size + chip->ecc.bytes * i;
218
219 return poi;
220}
221
222static inline int rk_nfc_data_len(struct nand_chip *chip)
223{
224 return chip->ecc.size + chip->ecc.bytes + NFC_SYS_DATA_SIZE;
225}
226
227static inline u8 *rk_nfc_data_ptr(struct nand_chip *chip, int i)
228{
229 struct rk_nfc *nfc = nand_get_controller_data(chip);
230
231 return nfc->page_buf + i * rk_nfc_data_len(chip);
232}
233
234static inline u8 *rk_nfc_oob_ptr(struct nand_chip *chip, int i)
235{
236 struct rk_nfc *nfc = nand_get_controller_data(chip);
237
238 return nfc->page_buf + i * rk_nfc_data_len(chip) + chip->ecc.size;
239}
240
241static int rk_nfc_hw_ecc_setup(struct nand_chip *chip, u32 strength)
242{
243 struct rk_nfc *nfc = nand_get_controller_data(chip);
244 u32 reg, i;
245
246 for (i = 0; i < NFC_ECC_MAX_MODES; i++) {
247 if (strength == nfc->cfg->ecc_strengths[i]) {
248 reg = nfc->cfg->ecc_cfgs[i];
249 break;
250 }
251 }
252
253 if (i >= NFC_ECC_MAX_MODES)
254 return -EINVAL;
255
256 writel(reg, nfc->regs + nfc->cfg->bchctl_off);
257
258 /* Save chip ECC setting */
259 nfc->cur_ecc = strength;
260
261 return 0;
262}
263
264static void rk_nfc_select_chip(struct mtd_info *mtd, int cs)
265{
266 struct nand_chip *chip = mtd_to_nand(mtd);
267 struct rk_nfc *nfc = nand_get_controller_data(chip);
268 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
269 struct nand_ecc_ctrl *ecc = &chip->ecc;
270 u32 val;
271
272 if (cs < 0) {
273 nfc->selected_bank = -1;
274 /* Deselect the currently selected target. */
275 val = readl(nfc->regs + NFC_FMCTL);
276 val &= ~FMCTL_CE_SEL_M;
277 writel(val, nfc->regs + NFC_FMCTL);
278 return;
279 }
280
281 nfc->selected_bank = rknand->sels[cs];
282 nfc->band_offset = NFC_BANK + nfc->selected_bank * NFC_BANK_STEP;
283
284 val = readl(nfc->regs + NFC_FMCTL);
285 val &= ~FMCTL_CE_SEL_M;
286 val |= FMCTL_CE_SEL(nfc->selected_bank);
287
288 writel(val, nfc->regs + NFC_FMCTL);
289
290 /*
291 * Compare current chip timing with selected chip timing and
292 * change if needed.
293 */
294 if (nfc->cur_timing != rknand->timing) {
295 writel(rknand->timing, nfc->regs + NFC_FMWAIT);
296 nfc->cur_timing = rknand->timing;
297 }
298
299 /*
300 * Compare current chip ECC setting with selected chip ECC setting and
301 * change if needed.
302 */
303 if (nfc->cur_ecc != ecc->strength)
304 rk_nfc_hw_ecc_setup(chip, ecc->strength);
305}
306
307static inline int rk_nfc_wait_ioready(struct rk_nfc *nfc)
308{
309 u32 timeout = (CONFIG_SYS_HZ * NFC_TIMEOUT_MS) / 1000;
310 u32 time_start;
311
312 time_start = get_timer(0);
313 do {
314 if (readl(nfc->regs + NFC_FMCTL) & FMCTL_RDY)
315 return 0;
316 } while (get_timer(time_start) < timeout);
317
318 dev_err(nfc->dev, "wait for io ready timedout\n");
319 return -ETIMEDOUT;
320}
321
322static void rk_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
323{
324 struct nand_chip *chip = mtd_to_nand(mtd);
325 struct rk_nfc *nfc = nand_get_controller_data(chip);
326 void __iomem *bank_base;
327 int i = 0;
328
329 bank_base = nfc->regs + nfc->band_offset + BANK_DATA;
330
331 for (i = 0; i < len; i++)
332 buf[i] = readl(bank_base);
333}
334
335static void rk_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
336{
337 struct nand_chip *chip = mtd_to_nand(mtd);
338 struct rk_nfc *nfc = nand_get_controller_data(chip);
339 void __iomem *bank_base;
340 int i = 0;
341
342 bank_base = nfc->regs + nfc->band_offset + BANK_DATA;
343
344 for (i = 0; i < len; i++)
345 writel(buf[i], bank_base);
346}
347
348static void rk_nfc_cmd(struct mtd_info *mtd, int dat, unsigned int ctrl)
349{
350 struct nand_chip *chip = mtd_to_nand(mtd);
351 struct rk_nfc *nfc = nand_get_controller_data(chip);
352 void __iomem *bank_base;
353
354 bank_base = nfc->regs + nfc->band_offset;
355
356 if (ctrl & NAND_CTRL_CHANGE) {
357 if (ctrl & NAND_ALE)
358 bank_base += BANK_ADDR;
359 else if (ctrl & NAND_CLE)
360 bank_base += BANK_CMD;
361 chip->IO_ADDR_W = bank_base;
362 }
363
364 if (dat != NAND_CMD_NONE)
365 writel(dat & 0xFF, chip->IO_ADDR_W);
366}
367
368static uint8_t rockchip_nand_read_byte(struct mtd_info *mtd)
369{
370 uint8_t ret;
371
372 rk_nfc_read_buf(mtd, &ret, 1);
373
374 return ret;
375}
376
377static int rockchip_nand_dev_ready(struct mtd_info *mtd)
378{
379 struct nand_chip *chip = mtd_to_nand(mtd);
380 struct rk_nfc *nfc = nand_get_controller_data(chip);
381
382 if (readl(nfc->regs + NFC_FMCTL) & FMCTL_RDY)
383 return 1;
384
385 return 0;
386}
387
388static void rk_nfc_xfer_start(struct rk_nfc *nfc, u8 rw, u8 n_KB,
389 dma_addr_t dma_data, dma_addr_t dma_oob)
390{
391 u32 dma_reg, fl_reg, bch_reg;
392
393 dma_reg = DMA_ST | ((!rw) << DMA_WR) | DMA_EN | (2 << DMA_AHB_SIZE) |
394 (7 << DMA_BURST_SIZE) | (16 << DMA_INC_NUM);
395
396 fl_reg = (rw << FLCTL_WR) | FLCTL_XFER_EN | FLCTL_ACORRECT |
397 (n_KB << FLCTL_XFER_SECTOR) | FLCTL_TOG_FIX;
398
399 if (nfc->cfg->type == NFC_V6 || nfc->cfg->type == NFC_V8) {
400 bch_reg = readl_relaxed(nfc->regs + nfc->cfg->bchctl_off);
401 bch_reg = (bch_reg & (~BCHCTL_BANK_M)) |
402 (nfc->selected_bank << BCHCTL_BANK);
403 writel(bch_reg, nfc->regs + nfc->cfg->bchctl_off);
404 }
405
406 writel(dma_reg, nfc->regs + nfc->cfg->dma_cfg_off);
407 writel((u32)dma_data, nfc->regs + nfc->cfg->dma_data_buf_off);
408 writel((u32)dma_oob, nfc->regs + nfc->cfg->dma_oob_buf_off);
409 writel(fl_reg, nfc->regs + nfc->cfg->flctl_off);
410 fl_reg |= FLCTL_XFER_ST;
411 writel(fl_reg, nfc->regs + nfc->cfg->flctl_off);
412}
413
414static int rk_nfc_wait_for_xfer_done(struct rk_nfc *nfc)
415{
416 unsigned long timeout = (CONFIG_SYS_HZ * NFC_TIMEOUT_MS) / 1000;
417 void __iomem *ptr = nfc->regs + nfc->cfg->flctl_off;
418 u32 time_start;
419
420 time_start = get_timer(0);
421
422 do {
423 if (readl(ptr) & FLCTL_XFER_READY)
424 return 0;
425 } while (get_timer(time_start) < timeout);
426
427 dev_err(nfc->dev, "wait for io ready timedout\n");
428 return -ETIMEDOUT;
429}
430
431static int rk_nfc_write_page_raw(struct mtd_info *mtd,
432 struct nand_chip *chip,
433 const u8 *buf,
434 int oob_required,
435 int page)
436{
437 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
438 struct rk_nfc *nfc = nand_get_controller_data(chip);
439 struct nand_ecc_ctrl *ecc = &chip->ecc;
440 int i, pages_per_blk;
441
442 pages_per_blk = mtd->erasesize / mtd->writesize;
443 if ((page < (pages_per_blk * rknand->boot_blks)) &&
444 rknand->boot_ecc != ecc->strength) {
445 /*
446 * There's currently no method to notify the MTD framework that
447 * a different ECC strength is in use for the boot blocks.
448 */
449 return -EIO;
450 }
451
452 if (!buf)
453 memset(nfc->page_buf, 0xff, mtd->writesize + mtd->oobsize);
454
455 for (i = 0; i < ecc->steps; i++) {
456 /* Copy data to the NFC buffer. */
457 if (buf)
458 memcpy(rk_nfc_data_ptr(chip, i),
459 rk_nfc_buf_to_data_ptr(chip, buf, i),
460 ecc->size);
461 /*
462 * The first four bytes of OOB are reserved for the
463 * boot ROM. In some debugging cases, such as with a
464 * read, erase and write back test these 4 bytes stored
465 * in OOB also need to be written back.
466 *
467 * The function nand_block_bad detects bad blocks like:
468 *
469 * bad = chip->oob_poi[chip->badblockpos];
470 *
471 * chip->badblockpos == 0 for a large page NAND Flash,
472 * so chip->oob_poi[0] is the bad block mask (BBM).
473 *
474 * The OOB data layout on the NFC is:
475 *
476 * PA0 PA1 PA2 PA3 | BBM OOB1 OOB2 OOB3 | ...
477 *
478 * or
479 *
480 * 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ...
481 *
482 * The code here just swaps the first 4 bytes with the last
483 * 4 bytes without losing any data.
484 *
485 * The chip->oob_poi data layout:
486 *
487 * BBM OOB1 OOB2 OOB3 |......| PA0 PA1 PA2 PA3
488 *
Johan Jonker6404ca62023-03-13 01:29:05 +0100489 * The oobfree structure already has reserved these 4 bytes
490 * together with 2 bytes for BBM by reducing it's length:
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800491 *
Johan Jonker6404ca62023-03-13 01:29:05 +0100492 * oobfree[0].length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2;
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800493 */
494 if (!i)
495 memcpy(rk_nfc_oob_ptr(chip, i),
496 rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1),
497 NFC_SYS_DATA_SIZE);
498 else
499 memcpy(rk_nfc_oob_ptr(chip, i),
500 rk_nfc_buf_to_oob_ptr(chip, i - 1),
501 NFC_SYS_DATA_SIZE);
502 /* Copy ECC data to the NFC buffer. */
503 memcpy(rk_nfc_oob_ptr(chip, i) + NFC_SYS_DATA_SIZE,
504 rk_nfc_buf_to_oob_ecc_ptr(chip, i),
505 ecc->bytes);
506 }
507
508 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
509 rk_nfc_write_buf(mtd, buf, mtd->writesize + mtd->oobsize);
510 return nand_prog_page_end_op(chip);
511}
512
513static int rk_nfc_write_page_hwecc(struct mtd_info *mtd,
514 struct nand_chip *chip,
515 const u8 *buf,
516 int oob_required,
517 int page)
518{
519 struct rk_nfc *nfc = nand_get_controller_data(chip);
520 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
521 struct nand_ecc_ctrl *ecc = &chip->ecc;
522 int oob_step = (ecc->bytes > 60) ? NFC_MAX_OOB_PER_STEP :
523 NFC_MIN_OOB_PER_STEP;
524 int pages_per_blk = mtd->erasesize / mtd->writesize;
525 int ret = 0, i, boot_rom_mode = 0;
526 dma_addr_t dma_data, dma_oob;
Johan Jonkercceb2382023-06-22 15:59:24 +0200527 u32 tmp;
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800528 u8 *oob;
529
530 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
531
532 if (buf)
533 memcpy(nfc->page_buf, buf, mtd->writesize);
534 else
535 memset(nfc->page_buf, 0xFF, mtd->writesize);
536
537 /*
538 * The first blocks (4, 8 or 16 depending on the device) are used
539 * by the boot ROM and the first 32 bits of OOB need to link to
540 * the next page address in the same block. We can't directly copy
541 * OOB data from the MTD framework, because this page address
542 * conflicts for example with the bad block marker (BBM),
543 * so we shift all OOB data including the BBM with 4 byte positions.
544 * As a consequence the OOB size available to the MTD framework is
545 * also reduced with 4 bytes.
546 *
547 * PA0 PA1 PA2 PA3 | BBM OOB1 OOB2 OOB3 | ...
548 *
549 * If a NAND is not a boot medium or the page is not a boot block,
550 * the first 4 bytes are left untouched by writing 0xFF to them.
551 *
552 * 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ...
553 *
Johan Jonkercceb2382023-06-22 15:59:24 +0200554 * The code here just swaps the first 4 bytes with the last
555 * 4 bytes without losing any data.
556 *
557 * The chip->oob_poi data layout:
558 *
559 * BBM OOB1 OOB2 OOB3 |......| PA0 PA1 PA2 PA3
560 *
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800561 * Configure the ECC algorithm supported by the boot ROM.
562 */
563 if (page < (pages_per_blk * rknand->boot_blks)) {
564 boot_rom_mode = 1;
565 if (rknand->boot_ecc != ecc->strength)
566 rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc);
567 }
568
569 for (i = 0; i < ecc->steps; i++) {
Johan Jonkercceb2382023-06-22 15:59:24 +0200570 if (!i)
571 oob = chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE;
572 else
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800573 oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800574
Johan Jonkercceb2382023-06-22 15:59:24 +0200575 tmp = oob[0] | oob[1] << 8 | oob[2] << 16 | oob[3] << 24;
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800576
577 if (nfc->cfg->type == NFC_V9)
Johan Jonkercceb2382023-06-22 15:59:24 +0200578 nfc->oob_buf[i] = tmp;
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800579 else
Johan Jonkercceb2382023-06-22 15:59:24 +0200580 nfc->oob_buf[i * (oob_step / 4)] = tmp;
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800581 }
582
583 dma_data = dma_map_single((void *)nfc->page_buf,
584 mtd->writesize, DMA_TO_DEVICE);
585 dma_oob = dma_map_single(nfc->oob_buf,
586 ecc->steps * oob_step,
587 DMA_TO_DEVICE);
588
589 rk_nfc_xfer_start(nfc, NFC_WRITE, ecc->steps, dma_data,
590 dma_oob);
591 ret = rk_nfc_wait_for_xfer_done(nfc);
592
593 dma_unmap_single(dma_data, mtd->writesize,
594 DMA_TO_DEVICE);
595 dma_unmap_single(dma_oob, ecc->steps * oob_step,
596 DMA_TO_DEVICE);
597
598 if (boot_rom_mode && rknand->boot_ecc != ecc->strength)
599 rk_nfc_hw_ecc_setup(chip, ecc->strength);
600
601 if (ret) {
602 dev_err(nfc->dev, "write: wait transfer done timeout.\n");
603 return -ETIMEDOUT;
604 }
605
606 return nand_prog_page_end_op(chip);
607}
608
609static int rk_nfc_write_oob(struct mtd_info *mtd,
610 struct nand_chip *chip, int page)
611{
612 return rk_nfc_write_page_hwecc(mtd, chip, NULL, 1, page);
613}
614
615static int rk_nfc_read_page_raw(struct mtd_info *mtd,
616 struct nand_chip *chip,
617 u8 *buf,
618 int oob_required,
619 int page)
620{
621 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
622 struct rk_nfc *nfc = nand_get_controller_data(chip);
623 struct nand_ecc_ctrl *ecc = &chip->ecc;
624 int i, pages_per_blk;
625
626 pages_per_blk = mtd->erasesize / mtd->writesize;
627 if ((page < (pages_per_blk * rknand->boot_blks)) &&
628 nfc->selected_bank == 0 &&
629 rknand->boot_ecc != ecc->strength) {
630 /*
631 * There's currently no method to notify the MTD framework that
632 * a different ECC strength is in use for the boot blocks.
633 */
634 return -EIO;
635 }
636
637 nand_read_page_op(chip, page, 0, NULL, 0);
638 rk_nfc_read_buf(mtd, nfc->page_buf, mtd->writesize + mtd->oobsize);
639 for (i = 0; i < ecc->steps; i++) {
640 /*
641 * The first four bytes of OOB are reserved for the
642 * boot ROM. In some debugging cases, such as with a read,
643 * erase and write back test, these 4 bytes also must be
644 * saved somewhere, otherwise this information will be
645 * lost during a write back.
646 */
647 if (!i)
648 memcpy(rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1),
649 rk_nfc_oob_ptr(chip, i),
650 NFC_SYS_DATA_SIZE);
651 else
652 memcpy(rk_nfc_buf_to_oob_ptr(chip, i - 1),
653 rk_nfc_oob_ptr(chip, i),
654 NFC_SYS_DATA_SIZE);
655
656 /* Copy ECC data from the NFC buffer. */
657 memcpy(rk_nfc_buf_to_oob_ecc_ptr(chip, i),
658 rk_nfc_oob_ptr(chip, i) + NFC_SYS_DATA_SIZE,
659 ecc->bytes);
660
661 /* Copy data from the NFC buffer. */
662 if (buf)
663 memcpy(rk_nfc_buf_to_data_ptr(chip, buf, i),
664 rk_nfc_data_ptr(chip, i),
665 ecc->size);
666 }
667
668 return 0;
669}
670
671static int rk_nfc_read_page_hwecc(struct mtd_info *mtd,
672 struct nand_chip *chip,
673 u8 *buf,
674 int oob_required,
675 int page)
676{
677 struct rk_nfc *nfc = nand_get_controller_data(chip);
678 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
679 struct nand_ecc_ctrl *ecc = &chip->ecc;
680 int oob_step = (ecc->bytes > 60) ? NFC_MAX_OOB_PER_STEP :
681 NFC_MIN_OOB_PER_STEP;
682 int pages_per_blk = mtd->erasesize / mtd->writesize;
683 dma_addr_t dma_data, dma_oob;
684 int ret = 0, i, cnt, boot_rom_mode = 0;
685 int max_bitflips = 0, bch_st, ecc_fail = 0;
686 u8 *oob;
687 u32 tmp;
688
689 nand_read_page_op(chip, page, 0, NULL, 0);
690
691 dma_data = dma_map_single(nfc->page_buf,
692 mtd->writesize,
693 DMA_FROM_DEVICE);
694 dma_oob = dma_map_single(nfc->oob_buf,
695 ecc->steps * oob_step,
696 DMA_FROM_DEVICE);
697
698 /*
699 * The first blocks (4, 8 or 16 depending on the device)
700 * are used by the boot ROM.
701 * Configure the ECC algorithm supported by the boot ROM.
702 */
703 if (page < (pages_per_blk * rknand->boot_blks) &&
704 nfc->selected_bank == 0) {
705 boot_rom_mode = 1;
706 if (rknand->boot_ecc != ecc->strength)
707 rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc);
708 }
709
710 rk_nfc_xfer_start(nfc, NFC_READ, ecc->steps, dma_data,
711 dma_oob);
712 ret = rk_nfc_wait_for_xfer_done(nfc);
713
714 dma_unmap_single(dma_data, mtd->writesize,
715 DMA_FROM_DEVICE);
716 dma_unmap_single(dma_oob, ecc->steps * oob_step,
717 DMA_FROM_DEVICE);
718
719 if (ret) {
720 ret = -ETIMEDOUT;
721 dev_err(nfc->dev, "read: wait transfer done timeout.\n");
722 goto timeout_err;
723 }
724
Johan Jonkercceb2382023-06-22 15:59:24 +0200725 for (i = 0; i < ecc->steps; i++) {
726 if (!i)
727 oob = chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE;
728 else
729 oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
730
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800731 if (nfc->cfg->type == NFC_V9)
732 tmp = nfc->oob_buf[i];
733 else
734 tmp = nfc->oob_buf[i * (oob_step / 4)];
Johan Jonkercceb2382023-06-22 15:59:24 +0200735
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800736 *oob++ = (u8)tmp;
737 *oob++ = (u8)(tmp >> 8);
738 *oob++ = (u8)(tmp >> 16);
739 *oob++ = (u8)(tmp >> 24);
740 }
741
742 for (i = 0; i < (ecc->steps / 2); i++) {
743 bch_st = readl_relaxed(nfc->regs +
744 nfc->cfg->bch_st_off + i * 4);
745 if (bch_st & BIT(nfc->cfg->ecc0.err_flag_bit) ||
746 bch_st & BIT(nfc->cfg->ecc1.err_flag_bit)) {
747 mtd->ecc_stats.failed++;
748 ecc_fail = 1;
749 } else {
750 cnt = ECC_ERR_CNT(bch_st, nfc->cfg->ecc0);
751 mtd->ecc_stats.corrected += cnt;
752 max_bitflips = max_t(u32, max_bitflips, cnt);
753
754 cnt = ECC_ERR_CNT(bch_st, nfc->cfg->ecc1);
755 mtd->ecc_stats.corrected += cnt;
756 max_bitflips = max_t(u32, max_bitflips, cnt);
757 }
758 }
759
760 if (buf)
761 memcpy(buf, nfc->page_buf, mtd->writesize);
762
763timeout_err:
764 if (boot_rom_mode && rknand->boot_ecc != ecc->strength)
765 rk_nfc_hw_ecc_setup(chip, ecc->strength);
766
767 if (ret)
768 return ret;
769
770 if (ecc_fail) {
771 dev_err(nfc->dev, "read page: %x ecc error!\n", page);
772 return 0;
773 }
774
775 return max_bitflips;
776}
777
778static int rk_nfc_read_oob(struct mtd_info *mtd,
779 struct nand_chip *chip, int page)
780{
781 return rk_nfc_read_page_hwecc(mtd, chip, NULL, 1, page);
782}
783
784static inline void rk_nfc_hw_init(struct rk_nfc *nfc)
785{
786 /* Disable flash wp. */
787 writel(FMCTL_WP, nfc->regs + NFC_FMCTL);
788 /* Config default timing 40ns at 150 Mhz NFC clock. */
789 writel(0x1081, nfc->regs + NFC_FMWAIT);
790 nfc->cur_timing = 0x1081;
791 /* Disable randomizer and DMA. */
792 writel(0, nfc->regs + nfc->cfg->randmz_off);
793 writel(0, nfc->regs + nfc->cfg->dma_cfg_off);
794 writel(FLCTL_RST, nfc->regs + nfc->cfg->flctl_off);
795}
796
797static int rk_nfc_enable_clks(struct udevice *dev, struct rk_nfc *nfc)
798{
799 int ret;
800
801 if (!IS_ERR(nfc->nfc_clk)) {
802 ret = clk_prepare_enable(nfc->nfc_clk);
803 if (ret)
804 dev_err(dev, "failed to enable NFC clk\n");
805 }
806
807 ret = clk_prepare_enable(nfc->ahb_clk);
808 if (ret) {
809 dev_err(dev, "failed to enable ahb clk\n");
810 if (!IS_ERR(nfc->nfc_clk))
811 clk_disable_unprepare(nfc->nfc_clk);
812 }
813
814 return 0;
815}
816
817static void rk_nfc_disable_clks(struct rk_nfc *nfc)
818{
819 if (!IS_ERR(nfc->nfc_clk))
820 clk_disable_unprepare(nfc->nfc_clk);
821 clk_disable_unprepare(nfc->ahb_clk);
822}
823
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800824static int rk_nfc_ecc_init(struct rk_nfc *nfc, struct nand_chip *chip)
825{
Johan Jonker65c43462023-03-13 01:28:39 +0100826 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800827 const u8 *strengths = nfc->cfg->ecc_strengths;
828 struct mtd_info *mtd = nand_to_mtd(chip);
829 struct nand_ecc_ctrl *ecc = &chip->ecc;
830 u8 max_strength, nfc_max_strength;
831 int i;
832
833 nfc_max_strength = nfc->cfg->ecc_strengths[0];
834 /* If optional dt settings not present. */
835 if (!ecc->size || !ecc->strength ||
836 ecc->strength > nfc_max_strength) {
837 chip->ecc.size = 1024;
838 ecc->steps = mtd->writesize / ecc->size;
839
840 /*
841 * HW ECC always requests the number of ECC bytes per 1024 byte
842 * blocks. The first 4 OOB bytes are reserved for sys data.
843 */
844 max_strength = ((mtd->oobsize / ecc->steps) - 4) * 8 /
845 fls(8 * 1024);
846 if (max_strength > nfc_max_strength)
847 max_strength = nfc_max_strength;
848
849 for (i = 0; i < 4; i++) {
850 if (max_strength >= strengths[i])
851 break;
852 }
853
854 if (i >= 4) {
855 dev_err(nfc->dev, "unsupported ECC strength\n");
856 return -EOPNOTSUPP;
857 }
858
859 ecc->strength = strengths[i];
860 }
861 ecc->steps = mtd->writesize / ecc->size;
862 ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * chip->ecc.size), 8);
863
Johan Jonker65c43462023-03-13 01:28:39 +0100864 if (ecc->bytes * ecc->steps > mtd->oobsize - rknand->metadata_size)
865 return -EINVAL;
866
867 ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
868 if (!ecc->layout)
869 return -ENOMEM;
870
871 ecc->layout->eccbytes = ecc->bytes * ecc->steps;
872
873 for (i = 0; i < ecc->layout->eccbytes; i++)
874 ecc->layout->eccpos[i] = rknand->metadata_size + i;
875
876 ecc->layout->oobfree[0].length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2;
Johan Jonker6404ca62023-03-13 01:29:05 +0100877 ecc->layout->oobfree[0].offset = 2;
Johan Jonker65c43462023-03-13 01:28:39 +0100878
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800879 return 0;
880}
881
882static int rk_nfc_nand_chip_init(ofnode node, struct rk_nfc *nfc, int devnum)
883{
884 struct rk_nfc_nand_chip *rknand;
885 struct udevice *dev = nfc->dev;
886 struct nand_ecc_ctrl *ecc;
887 struct nand_chip *chip;
888 struct mtd_info *mtd;
889 u32 cs[NFC_MAX_NSELS];
890 int nsels, i, ret;
891 u32 tmp;
892
893 if (!ofnode_get_property(node, "reg", &nsels))
894 return -ENODEV;
895 nsels /= sizeof(u32);
896 if (!nsels || nsels > NFC_MAX_NSELS) {
897 dev_err(dev, "invalid reg property size %d\n", nsels);
898 return -EINVAL;
899 }
900
901 rknand = kzalloc(sizeof(*rknand) + nsels * sizeof(u8), GFP_KERNEL);
902 if (!rknand)
903 return -ENOMEM;
904
905 rknand->nsels = nsels;
906 rknand->timing = nfc->cur_timing;
907
908 ret = ofnode_read_u32_array(node, "reg", cs, nsels);
909 if (ret < 0) {
910 dev_err(dev, "Could not retrieve reg property\n");
911 return -EINVAL;
912 }
913
914 for (i = 0; i < nsels; i++) {
915 if (cs[i] >= NFC_MAX_NSELS) {
916 dev_err(dev, "invalid CS: %u\n", cs[i]);
917 return -EINVAL;
918 }
919
920 if (test_and_set_bit(cs[i], &nfc->assigned_cs)) {
921 dev_err(dev, "CS %u already assigned\n", cs[i]);
922 return -EINVAL;
923 }
924
925 rknand->sels[i] = cs[i];
926 }
927
928 chip = &rknand->chip;
929 ecc = &chip->ecc;
930 ecc->mode = NAND_ECC_HW_SYNDROME;
931
932 ret = ofnode_read_u32(node, "nand-ecc-strength", &tmp);
933 ecc->strength = ret ? 0 : tmp;
934
935 ret = ofnode_read_u32(node, "nand-ecc-step-size", &tmp);
936 ecc->size = ret ? 0 : tmp;
937
938 mtd = nand_to_mtd(chip);
939 mtd->owner = THIS_MODULE;
940 mtd->dev->parent = dev;
941
942 nand_set_controller_data(chip, nfc);
943
Johan Jonkerfb1ab9f2023-03-13 01:28:53 +0100944 chip->flash_node = node;
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800945 chip->chip_delay = NFC_RB_DELAY_US;
946 chip->select_chip = rk_nfc_select_chip;
947 chip->cmd_ctrl = rk_nfc_cmd;
948 chip->read_buf = rk_nfc_read_buf;
949 chip->write_buf = rk_nfc_write_buf;
950 chip->read_byte = rockchip_nand_read_byte;
951 chip->dev_ready = rockchip_nand_dev_ready;
952 chip->controller = &nfc->controller;
953
954 chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
955 chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
956
Johan Jonker904e0f02023-10-18 16:00:27 +0200957 if (IS_ENABLED(CONFIG_ROCKCHIP_NAND_SKIP_BBTSCAN))
958 chip->options |= NAND_SKIP_BBTSCAN;
959
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800960 rk_nfc_hw_init(nfc);
961 ret = nand_scan_ident(mtd, nsels, NULL);
962 if (ret)
963 return ret;
964
965 ret = rk_nfc_ecc_init(nfc, chip);
966 if (ret) {
967 dev_err(dev, "rk_nfc_ecc_init failed: %d\n", ret);
968 return ret;
969 }
970
971 ret = ofnode_read_u32(node, "rockchip,boot-blks", &tmp);
972 rknand->boot_blks = ret ? 0 : tmp;
973
974 ret = ofnode_read_u32(node, "rockchip,boot-ecc-strength", &tmp);
975 rknand->boot_ecc = ret ? ecc->strength : tmp;
976
977 rknand->metadata_size = NFC_SYS_DATA_SIZE * ecc->steps;
978
979 if (rknand->metadata_size < NFC_SYS_DATA_SIZE + 2) {
980 dev_err(dev,
981 "driver needs at least %d bytes of meta data\n",
982 NFC_SYS_DATA_SIZE + 2);
983 return -EIO;
984 }
985
986 if (!nfc->page_buf) {
987 nfc->page_buf = kzalloc(NFC_MAX_PAGE_SIZE, GFP_KERNEL);
Johan Jonker65c43462023-03-13 01:28:39 +0100988 if (!nfc->page_buf) {
989 kfree(ecc->layout);
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800990 return -ENOMEM;
Johan Jonker65c43462023-03-13 01:28:39 +0100991 }
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800992 }
993
994 if (!nfc->oob_buf) {
995 nfc->oob_buf = kzalloc(NFC_MAX_OOB_SIZE, GFP_KERNEL);
996 if (!nfc->oob_buf) {
Johan Jonker65c43462023-03-13 01:28:39 +0100997 kfree(ecc->layout);
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800998 kfree(nfc->page_buf);
999 nfc->page_buf = NULL;
1000 return -ENOMEM;
1001 }
1002 }
1003
1004 ecc->read_page = rk_nfc_read_page_hwecc;
1005 ecc->read_page_raw = rk_nfc_read_page_raw;
1006 ecc->read_oob = rk_nfc_read_oob;
1007 ecc->write_page = rk_nfc_write_page_hwecc;
1008 ecc->write_page_raw = rk_nfc_write_page_raw;
1009 ecc->write_oob = rk_nfc_write_oob;
1010
1011 ret = nand_scan_tail(mtd);
1012 if (ret) {
1013 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
1014 return ret;
1015 }
1016
1017 return nand_register(devnum, mtd);
1018}
1019
1020static int rk_nfc_nand_chips_init(struct udevice *dev, struct rk_nfc *nfc)
1021{
1022 int ret, i = 0;
1023 ofnode child;
1024
1025 ofnode_for_each_subnode(child, dev_ofnode(dev)) {
1026 ret = rk_nfc_nand_chip_init(child, nfc, i++);
1027 if (ret)
1028 return ret;
1029 }
1030
1031 return 0;
1032}
1033
1034static struct nfc_cfg nfc_v6_cfg = {
1035 .type = NFC_V6,
1036 .ecc_strengths = {60, 40, 24, 16},
1037 .ecc_cfgs = {
1038 0x00040011, 0x00040001, 0x00000011, 0x00000001,
1039 },
1040 .flctl_off = 0x08,
1041 .bchctl_off = 0x0C,
1042 .dma_cfg_off = 0x10,
1043 .dma_data_buf_off = 0x14,
1044 .dma_oob_buf_off = 0x18,
1045 .dma_st_off = 0x1C,
1046 .bch_st_off = 0x20,
1047 .randmz_off = 0x150,
1048 .int_en_off = 0x16C,
1049 .int_clr_off = 0x170,
1050 .int_st_off = 0x174,
1051 .oob0_off = 0x200,
1052 .oob1_off = 0x230,
1053 .ecc0 = {
1054 .err_flag_bit = 2,
1055 .low = 3,
1056 .low_mask = 0x1F,
1057 .low_bn = 5,
1058 .high = 27,
1059 .high_mask = 0x1,
1060 },
1061 .ecc1 = {
1062 .err_flag_bit = 15,
1063 .low = 16,
1064 .low_mask = 0x1F,
1065 .low_bn = 5,
1066 .high = 29,
1067 .high_mask = 0x1,
1068 },
1069};
1070
1071static struct nfc_cfg nfc_v8_cfg = {
1072 .type = NFC_V8,
1073 .ecc_strengths = {16, 16, 16, 16},
1074 .ecc_cfgs = {
1075 0x00000001, 0x00000001, 0x00000001, 0x00000001,
1076 },
1077 .flctl_off = 0x08,
1078 .bchctl_off = 0x0C,
1079 .dma_cfg_off = 0x10,
1080 .dma_data_buf_off = 0x14,
1081 .dma_oob_buf_off = 0x18,
1082 .dma_st_off = 0x1C,
1083 .bch_st_off = 0x20,
1084 .randmz_off = 0x150,
1085 .int_en_off = 0x16C,
1086 .int_clr_off = 0x170,
1087 .int_st_off = 0x174,
1088 .oob0_off = 0x200,
1089 .oob1_off = 0x230,
1090 .ecc0 = {
1091 .err_flag_bit = 2,
1092 .low = 3,
1093 .low_mask = 0x1F,
1094 .low_bn = 5,
1095 .high = 27,
1096 .high_mask = 0x1,
1097 },
1098 .ecc1 = {
1099 .err_flag_bit = 15,
1100 .low = 16,
1101 .low_mask = 0x1F,
1102 .low_bn = 5,
1103 .high = 29,
1104 .high_mask = 0x1,
1105 },
1106};
1107
1108static struct nfc_cfg nfc_v9_cfg = {
1109 .type = NFC_V9,
1110 .ecc_strengths = {70, 60, 40, 16},
1111 .ecc_cfgs = {
1112 0x00000001, 0x06000001, 0x04000001, 0x02000001,
1113 },
1114 .flctl_off = 0x10,
1115 .bchctl_off = 0x20,
1116 .dma_cfg_off = 0x30,
1117 .dma_data_buf_off = 0x34,
1118 .dma_oob_buf_off = 0x38,
1119 .dma_st_off = 0x3C,
1120 .bch_st_off = 0x150,
1121 .randmz_off = 0x208,
1122 .int_en_off = 0x120,
1123 .int_clr_off = 0x124,
1124 .int_st_off = 0x128,
1125 .oob0_off = 0x200,
1126 .oob1_off = 0x204,
1127 .ecc0 = {
1128 .err_flag_bit = 2,
1129 .low = 3,
1130 .low_mask = 0x7F,
1131 .low_bn = 7,
1132 .high = 0,
1133 .high_mask = 0x0,
1134 },
1135 .ecc1 = {
1136 .err_flag_bit = 18,
1137 .low = 19,
1138 .low_mask = 0x7F,
1139 .low_bn = 7,
1140 .high = 0,
1141 .high_mask = 0x0,
1142 },
1143};
1144
1145static const struct udevice_id rk_nfc_id_table[] = {
1146 {
1147 .compatible = "rockchip,px30-nfc",
1148 .data = (unsigned long)&nfc_v9_cfg
1149 },
1150 {
1151 .compatible = "rockchip,rk2928-nfc",
1152 .data = (unsigned long)&nfc_v6_cfg
1153 },
1154 {
1155 .compatible = "rockchip,rv1108-nfc",
1156 .data = (unsigned long)&nfc_v8_cfg
1157 },
Yifeng Zhao9e9021e2021-06-07 16:40:29 +08001158 { /* sentinel */ }
1159};
1160
1161static int rk_nfc_probe(struct udevice *dev)
1162{
1163 struct rk_nfc *nfc = dev_get_priv(dev);
1164 int ret = 0;
1165
1166 nfc->cfg = (void *)dev_get_driver_data(dev);
1167 nfc->dev = dev;
1168
Johan Jonkera433de02023-03-13 01:28:06 +01001169 nfc->regs = dev_read_addr_ptr(dev);
1170 if (!nfc->regs) {
1171 ret = -EINVAL;
Yifeng Zhao9e9021e2021-06-07 16:40:29 +08001172 goto release_nfc;
1173 }
1174
1175 nfc->nfc_clk = devm_clk_get(dev, "nfc");
1176 if (IS_ERR(nfc->nfc_clk)) {
1177 dev_dbg(dev, "no NFC clk\n");
1178 /* Some earlier models, such as rk3066, have no NFC clk. */
1179 }
1180
1181 nfc->ahb_clk = devm_clk_get(dev, "ahb");
1182 if (IS_ERR(nfc->ahb_clk)) {
1183 dev_err(dev, "no ahb clk\n");
1184 ret = PTR_ERR(nfc->ahb_clk);
1185 goto release_nfc;
1186 }
1187
1188 ret = rk_nfc_enable_clks(dev, nfc);
1189 if (ret)
1190 goto release_nfc;
1191
1192 spin_lock_init(&nfc->controller.lock);
1193 init_waitqueue_head(&nfc->controller.wq);
1194
1195 rk_nfc_hw_init(nfc);
1196
1197 ret = rk_nfc_nand_chips_init(dev, nfc);
1198 if (ret) {
1199 dev_err(dev, "failed to init NAND chips\n");
1200 goto clk_disable;
1201 }
1202 return 0;
1203
1204clk_disable:
1205 rk_nfc_disable_clks(nfc);
1206release_nfc:
1207 return ret;
1208}
1209
1210U_BOOT_DRIVER(rockchip_nfc) = {
1211 .name = "rockchip_nfc",
1212 .id = UCLASS_MTD,
1213 .of_match = rk_nfc_id_table,
1214 .probe = rk_nfc_probe,
1215 .priv_auto = sizeof(struct rk_nfc),
1216};
1217
1218void board_nand_init(void)
1219{
1220 struct udevice *dev;
1221 int ret;
1222
1223 ret = uclass_get_device_by_driver(UCLASS_MTD,
1224 DM_DRIVER_GET(rockchip_nfc),
1225 &dev);
1226 if (ret && ret != -ENODEV)
1227 log_err("Failed to initialize ROCKCHIP NAND controller. (error %d)\n",
1228 ret);
1229}
1230
1231int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
1232{
1233 struct mtd_info *mtd;
1234 size_t length = size;
1235
1236 mtd = get_nand_dev_by_index(0);
1237 return nand_read_skip_bad(mtd, offs, &length, NULL, size, (u_char *)dst);
1238}
1239
1240void nand_deselect(void) {}