Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
Tien Fong Chee | 851c724 | 2022-04-27 12:52:42 +0800 | [diff] [blame] | 3 | * Copyright (C) 2016-2022 Intel Corporation <www.intel.com> |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 4 | * |
| 5 | */ |
| 6 | |
Simon Glass | 1d91ba7 | 2019-11-14 12:57:37 -0700 | [diff] [blame] | 7 | #include <cpu_func.h> |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 8 | #include <dm.h> |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 9 | #include <errno.h> |
| 10 | #include <div64.h> |
Ley Foon Tan | 4bbed7b | 2019-03-22 01:24:01 +0800 | [diff] [blame] | 11 | #include <fdtdec.h> |
Simon Glass | f11478f | 2019-12-28 10:45:07 -0700 | [diff] [blame] | 12 | #include <hang.h> |
Simon Glass | 8e16b1e | 2019-12-28 10:45:05 -0700 | [diff] [blame] | 13 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 14 | #include <log.h> |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 15 | #include <ram.h> |
| 16 | #include <reset.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 17 | #include <asm/global_data.h> |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 18 | #include "sdram_s10.h" |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 19 | #include <wait_bit.h> |
Ley Foon Tan | f1c4bd5 | 2019-11-27 15:55:15 +0800 | [diff] [blame] | 20 | #include <asm/arch/firewall.h> |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 21 | #include <asm/arch/reset_manager.h> |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 22 | #include <asm/io.h> |
Ley Foon Tan | 4bbed7b | 2019-03-22 01:24:01 +0800 | [diff] [blame] | 23 | #include <linux/sizes.h> |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 24 | |
| 25 | DECLARE_GLOBAL_DATA_PTR; |
| 26 | |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 27 | #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) |
| 28 | |
| 29 | /* The followring are the supported configurations */ |
| 30 | u32 ddr_config[] = { |
| 31 | /* DDR_CONFIG(Address order,Bank,Column,Row) */ |
| 32 | /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */ |
| 33 | DDR_CONFIG(0, 3, 10, 12), |
| 34 | DDR_CONFIG(0, 3, 9, 13), |
| 35 | DDR_CONFIG(0, 3, 10, 13), |
| 36 | DDR_CONFIG(0, 3, 9, 14), |
| 37 | DDR_CONFIG(0, 3, 10, 14), |
| 38 | DDR_CONFIG(0, 3, 10, 15), |
| 39 | DDR_CONFIG(0, 3, 11, 14), |
| 40 | DDR_CONFIG(0, 3, 11, 15), |
| 41 | DDR_CONFIG(0, 3, 10, 16), |
| 42 | DDR_CONFIG(0, 3, 11, 16), |
| 43 | DDR_CONFIG(0, 3, 12, 15), /* 0xa */ |
| 44 | /* List for DDR4 only (pinout order > chip, bank, row, column) */ |
| 45 | DDR_CONFIG(1, 3, 10, 14), |
| 46 | DDR_CONFIG(1, 4, 10, 14), |
| 47 | DDR_CONFIG(1, 3, 10, 15), |
| 48 | DDR_CONFIG(1, 4, 10, 15), |
| 49 | DDR_CONFIG(1, 3, 10, 16), |
| 50 | DDR_CONFIG(1, 4, 10, 16), |
| 51 | DDR_CONFIG(1, 3, 10, 17), |
| 52 | DDR_CONFIG(1, 4, 10, 17), |
| 53 | }; |
| 54 | |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 55 | int match_ddr_conf(u32 ddr_conf) |
| 56 | { |
| 57 | int i; |
| 58 | |
| 59 | for (i = 0; i < ARRAY_SIZE(ddr_config); i++) { |
| 60 | if (ddr_conf == ddr_config[i]) |
| 61 | return i; |
| 62 | } |
| 63 | return 0; |
| 64 | } |
| 65 | |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 66 | /** |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 67 | * sdram_mmr_init_full() - Function to initialize SDRAM MMR |
| 68 | * |
| 69 | * Initialize the SDRAM MMR. |
| 70 | */ |
Ley Foon Tan | 25572cf | 2019-11-27 15:55:26 +0800 | [diff] [blame] | 71 | int sdram_mmr_init_full(struct udevice *dev) |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 72 | { |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 73 | struct altera_sdram_plat *plat = dev_get_plat(dev); |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 74 | struct altera_sdram_priv *priv = dev_get_priv(dev); |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 75 | u32 update_value, io48_value, ddrioctl; |
| 76 | u32 i; |
| 77 | int ret; |
Ley Foon Tan | 4bbed7b | 2019-03-22 01:24:01 +0800 | [diff] [blame] | 78 | phys_size_t hw_size; |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 79 | struct bd_info bd = {0}; |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 80 | |
| 81 | /* Enable access to DDR from CPU master */ |
| 82 | clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG), |
| 83 | CCU_ADBASE_DI_MASK); |
| 84 | clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0), |
| 85 | CCU_ADBASE_DI_MASK); |
| 86 | clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A), |
| 87 | CCU_ADBASE_DI_MASK); |
| 88 | clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B), |
| 89 | CCU_ADBASE_DI_MASK); |
| 90 | clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C), |
| 91 | CCU_ADBASE_DI_MASK); |
| 92 | clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D), |
| 93 | CCU_ADBASE_DI_MASK); |
| 94 | clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E), |
| 95 | CCU_ADBASE_DI_MASK); |
| 96 | |
| 97 | /* Enable access to DDR from IO master */ |
| 98 | clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0), |
| 99 | CCU_ADBASE_DI_MASK); |
| 100 | clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A), |
| 101 | CCU_ADBASE_DI_MASK); |
| 102 | clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B), |
| 103 | CCU_ADBASE_DI_MASK); |
| 104 | clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C), |
| 105 | CCU_ADBASE_DI_MASK); |
| 106 | clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D), |
| 107 | CCU_ADBASE_DI_MASK); |
| 108 | clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E), |
| 109 | CCU_ADBASE_DI_MASK); |
| 110 | |
Thor Thayer | 6e762d8 | 2019-12-06 13:47:31 -0600 | [diff] [blame] | 111 | /* Enable access to DDR from TCU */ |
| 112 | clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0), |
| 113 | CCU_ADBASE_DI_MASK); |
| 114 | clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A), |
| 115 | CCU_ADBASE_DI_MASK); |
| 116 | clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B), |
| 117 | CCU_ADBASE_DI_MASK); |
| 118 | clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C), |
| 119 | CCU_ADBASE_DI_MASK); |
| 120 | clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D), |
| 121 | CCU_ADBASE_DI_MASK); |
| 122 | clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E), |
| 123 | CCU_ADBASE_DI_MASK); |
| 124 | |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 125 | /* this enables nonsecure access to DDR */ |
| 126 | /* mpuregion0addr_limit */ |
| 127 | FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT); |
| 128 | FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT); |
| 129 | |
| 130 | /* nonmpuregion0addr_limit */ |
| 131 | FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, |
| 132 | FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); |
| 133 | FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT); |
| 134 | |
| 135 | /* Enable mpuregion0enable and nonmpuregion0enable */ |
| 136 | FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE, |
| 137 | FW_MPU_DDR_SCR_EN_SET); |
| 138 | |
| 139 | /* Ensure HMC clock is running */ |
| 140 | if (poll_hmc_clock_status()) { |
| 141 | puts("DDR: Error as HMC clock not running\n"); |
| 142 | return -1; |
| 143 | } |
| 144 | |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 145 | /* Try 3 times to do a calibration */ |
| 146 | for (i = 0; i < 3; i++) { |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 147 | ret = wait_for_bit_le32((const void *)(plat->hmc + |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 148 | DDRCALSTAT), |
| 149 | DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000, |
| 150 | false); |
| 151 | if (!ret) |
| 152 | break; |
| 153 | |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 154 | emif_reset(plat); |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | if (ret) { |
| 158 | puts("DDR: Error as SDRAM calibration failed\n"); |
| 159 | return -1; |
| 160 | } |
| 161 | debug("DDR: Calibration success\n"); |
| 162 | |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 163 | u32 ctrlcfg0 = hmc_readl(plat, CTRLCFG0); |
| 164 | u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1); |
| 165 | u32 dramaddrw = hmc_readl(plat, DRAMADDRW); |
| 166 | u32 dramtim0 = hmc_readl(plat, DRAMTIMING0); |
| 167 | u32 caltim0 = hmc_readl(plat, CALTIMING0); |
| 168 | u32 caltim1 = hmc_readl(plat, CALTIMING1); |
| 169 | u32 caltim2 = hmc_readl(plat, CALTIMING2); |
| 170 | u32 caltim3 = hmc_readl(plat, CALTIMING3); |
| 171 | u32 caltim4 = hmc_readl(plat, CALTIMING4); |
| 172 | u32 caltim9 = hmc_readl(plat, CALTIMING9); |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 173 | |
| 174 | /* |
| 175 | * Configure the DDR IO size [0xFFCFB008] |
| 176 | * niosreserve0: Used to indicate DDR width & |
| 177 | * bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit) |
| 178 | * bit[8] = 1 if user-mode OCT is present |
| 179 | * bit[9] = 1 if warm reset compiled into EMIF Cal Code |
| 180 | * bit[10] = 1 if warm reset is on during generation in EMIF Cal |
| 181 | * niosreserve1: IP ADCDS version encoded as 16 bit value |
| 182 | * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta, |
| 183 | * 3=EAP, 4-6 are reserved) |
| 184 | * bit[5:3] = Service Pack # (e.g. 1) |
| 185 | * bit[9:6] = Minor Release # |
| 186 | * bit[14:10] = Major Release # |
| 187 | */ |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 188 | update_value = hmc_readl(plat, NIOSRESERVED0); |
| 189 | hmc_ecc_writel(plat, ((update_value & 0xFF) >> 5), DDRIOCTRL); |
| 190 | ddrioctl = hmc_ecc_readl(plat, DDRIOCTRL); |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 191 | |
| 192 | /* enable HPS interface to HMC */ |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 193 | hmc_ecc_writel(plat, DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL); |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 194 | |
| 195 | /* Set the DDR Configuration */ |
| 196 | io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1), |
| 197 | (DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + |
| 198 | DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw)), |
| 199 | DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw), |
| 200 | DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw)); |
| 201 | |
| 202 | update_value = match_ddr_conf(io48_value); |
| 203 | if (update_value) |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 204 | ddr_sch_writel(plat, update_value, DDR_SCH_DDRCONF); |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 205 | |
| 206 | /* Configure HMC dramaddrw */ |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 207 | hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH); |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 208 | |
| 209 | /* |
| 210 | * Configure DDR timing |
| 211 | * RDTOMISS = tRTP + tRP + tRCD - BL/2 |
| 212 | * WRTOMISS = WL + tWR + tRP + tRCD and |
| 213 | * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so... |
| 214 | * First part of equation is in memory clock units so divide by 2 |
| 215 | * for HMC clock units. 1066MHz is close to 1ns so use 15 directly. |
| 216 | * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD |
| 217 | */ |
| 218 | u32 burst_len = CTRLCFG0_CFG_CTRL_BURST_LEN(ctrlcfg0); |
| 219 | |
| 220 | update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) + |
| 221 | CALTIMING4_CFG_PCH_TO_VALID(caltim4) + |
| 222 | CALTIMING0_CFG_ACT_TO_RDWR(caltim0) - |
| 223 | (burst_len >> 2); |
| 224 | io48_value = (((DRAMTIMING0_CFG_TCL(dramtim0) + 2 + DDR_TWR + |
| 225 | (burst_len >> 1)) >> 1) - |
| 226 | /* Up to here was in memory cycles so divide by 2 */ |
| 227 | CALTIMING1_CFG_RD_TO_WR(caltim1) + |
| 228 | CALTIMING0_CFG_ACT_TO_RDWR(caltim0) + |
| 229 | CALTIMING4_CFG_PCH_TO_VALID(caltim4)); |
| 230 | |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 231 | ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT(caltim0) << |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 232 | DDR_SCH_DDRTIMING_ACTTOACT_OFF) | |
| 233 | (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) | |
| 234 | (io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) | |
| 235 | ((burst_len >> 2) << DDR_SCH_DDRTIMING_BURSTLEN_OFF) | |
| 236 | (CALTIMING1_CFG_RD_TO_WR(caltim1) << |
| 237 | DDR_SCH_DDRTIMING_RDTOWR_OFF) | |
| 238 | (CALTIMING3_CFG_WR_TO_RD(caltim3) << |
| 239 | DDR_SCH_DDRTIMING_WRTORD_OFF) | |
| 240 | (((ddrioctl == 1) ? 1 : 0) << |
| 241 | DDR_SCH_DDRTIMING_BWRATIO_OFF)), |
| 242 | DDR_SCH_DDRTIMING); |
| 243 | |
| 244 | /* Configure DDR mode [precharge = 0] */ |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 245 | ddr_sch_writel(plat, ((ddrioctl ? 0 : 1) << |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 246 | DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF), |
| 247 | DDR_SCH_DDRMODE); |
| 248 | |
| 249 | /* Configure the read latency */ |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 250 | ddr_sch_writel(plat, (DRAMTIMING0_CFG_TCL(dramtim0) >> 1) + |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 251 | DDR_READ_LATENCY_DELAY, |
| 252 | DDR_SCH_READ_LATENCY); |
| 253 | |
| 254 | /* |
| 255 | * Configuring timing values concerning activate commands |
| 256 | * [FAWBANK alway 1 because always 4 bank DDR] |
| 257 | */ |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 258 | ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) << |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 259 | DDR_SCH_ACTIVATE_RRD_OFF) | |
| 260 | (CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) << |
| 261 | DDR_SCH_ACTIVATE_FAW_OFF) | |
| 262 | (DDR_ACTIVATE_FAWBANK << |
| 263 | DDR_SCH_ACTIVATE_FAWBANK_OFF)), |
| 264 | DDR_SCH_ACTIVATE); |
| 265 | |
| 266 | /* |
| 267 | * Configuring timing values concerning device to device data bus |
| 268 | * ownership change |
| 269 | */ |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 270 | ddr_sch_writel(plat, ((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) << |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 271 | DDR_SCH_DEVTODEV_BUSRDTORD_OFF) | |
| 272 | (CALTIMING1_CFG_RD_TO_WR_DC(caltim1) << |
| 273 | DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) | |
| 274 | (CALTIMING3_CFG_WR_TO_RD_DC(caltim3) << |
| 275 | DDR_SCH_DEVTODEV_BUSWRTORD_OFF)), |
| 276 | DDR_SCH_DEVTODEV); |
| 277 | |
| 278 | /* assigning the SDRAM size */ |
Tien Fong Chee | 851c724 | 2022-04-27 12:52:42 +0800 | [diff] [blame] | 279 | phys_size_t size = sdram_calculate_size(plat); |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 280 | /* If the size is invalid, use default Config size */ |
| 281 | if (size <= 0) |
Ley Foon Tan | 4bbed7b | 2019-03-22 01:24:01 +0800 | [diff] [blame] | 282 | hw_size = PHYS_SDRAM_1_SIZE; |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 283 | else |
Ley Foon Tan | 4bbed7b | 2019-03-22 01:24:01 +0800 | [diff] [blame] | 284 | hw_size = size; |
| 285 | |
| 286 | /* Get bank configuration from devicetree */ |
| 287 | ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, |
| 288 | (phys_size_t *)&gd->ram_size, &bd); |
| 289 | if (ret) { |
| 290 | puts("DDR: Failed to decode memory node\n"); |
| 291 | return -1; |
| 292 | } |
| 293 | |
| 294 | if (gd->ram_size != hw_size) |
| 295 | printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n"); |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 296 | |
Ley Foon Tan | a9245d1 | 2019-03-22 01:24:00 +0800 | [diff] [blame] | 297 | printf("DDR: %lld MiB\n", gd->ram_size >> 20); |
| 298 | |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 299 | /* Enable or disable the SDRAM ECC */ |
| 300 | if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) { |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 301 | setbits_le32(plat->hmc + ECCCTRL1, |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 302 | (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | |
| 303 | DDR_HMC_ECCCTL_CNT_RST_SET_MSK | |
| 304 | DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 305 | clrbits_le32(plat->hmc + ECCCTRL1, |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 306 | (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | |
| 307 | DDR_HMC_ECCCTL_CNT_RST_SET_MSK)); |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 308 | setbits_le32(plat->hmc + ECCCTRL2, |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 309 | (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | |
| 310 | DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 311 | hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS); |
Ley Foon Tan | 9799a67 | 2019-03-22 01:24:05 +0800 | [diff] [blame] | 312 | |
Ley Foon Tan | 9799a67 | 2019-03-22 01:24:05 +0800 | [diff] [blame] | 313 | /* Initialize memory content if not from warm reset */ |
| 314 | if (!cpu_has_been_warmreset()) |
| 315 | sdram_init_ecc_bits(&bd); |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 316 | } else { |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 317 | clrbits_le32(plat->hmc + ECCCTRL1, |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 318 | (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | |
| 319 | DDR_HMC_ECCCTL_CNT_RST_SET_MSK | |
| 320 | DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 321 | clrbits_le32(plat->hmc + ECCCTRL2, |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 322 | (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | |
| 323 | DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); |
| 324 | } |
| 325 | |
Thor Thayer | 7ead421 | 2019-12-06 13:47:32 -0600 | [diff] [blame] | 326 | /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */ |
| 327 | writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); |
| 328 | |
Ley Foon Tan | 4bbed7b | 2019-03-22 01:24:01 +0800 | [diff] [blame] | 329 | sdram_size_check(&bd); |
Ley Foon Tan | a9245d1 | 2019-03-22 01:24:00 +0800 | [diff] [blame] | 330 | |
Ley Foon Tan | 3fdf436 | 2019-05-06 09:56:01 +0800 | [diff] [blame] | 331 | priv->info.base = bd.bi_dram[0].start; |
| 332 | priv->info.size = gd->ram_size; |
| 333 | |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 334 | debug("DDR: HMC init success\n"); |
| 335 | return 0; |
| 336 | } |