Peng Fan | d69d0a6 | 2019-08-19 07:54:01 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright 2019 NXP |
| 4 | */ |
| 5 | |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 6 | #include <log.h> |
Peng Fan | d69d0a6 | 2019-08-19 07:54:01 +0000 | [diff] [blame] | 7 | #include <asm/io.h> |
| 8 | #include <malloc.h> |
| 9 | #include <clk-uclass.h> |
| 10 | #include <dm/device.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 11 | #include <dm/devres.h> |
Peng Fan | d69d0a6 | 2019-08-19 07:54:01 +0000 | [diff] [blame] | 12 | #include <linux/clk-provider.h> |
| 13 | #include <clk.h> |
| 14 | #include "clk.h" |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 15 | #include <linux/err.h> |
Peng Fan | d69d0a6 | 2019-08-19 07:54:01 +0000 | [diff] [blame] | 16 | |
| 17 | #define UBOOT_DM_CLK_IMX_COMPOSITE "imx_clk_composite" |
| 18 | |
| 19 | #define PCG_PREDIV_SHIFT 16 |
| 20 | #define PCG_PREDIV_WIDTH 3 |
| 21 | #define PCG_PREDIV_MAX 8 |
| 22 | |
| 23 | #define PCG_DIV_SHIFT 0 |
| 24 | #define PCG_DIV_WIDTH 6 |
| 25 | #define PCG_DIV_MAX 64 |
| 26 | |
| 27 | #define PCG_PCS_SHIFT 24 |
| 28 | #define PCG_PCS_MASK 0x7 |
| 29 | |
| 30 | #define PCG_CGC_SHIFT 28 |
| 31 | |
| 32 | static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk *clk) |
| 33 | { |
| 34 | struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk); |
| 35 | struct clk_composite *composite = (struct clk_composite *)clk->data; |
| 36 | ulong parent_rate = clk_get_parent_rate(&composite->clk); |
| 37 | unsigned long prediv_rate; |
| 38 | unsigned int prediv_value; |
| 39 | unsigned int div_value; |
| 40 | |
| 41 | debug("%s: name %s prate: %lu reg: %p\n", __func__, |
| 42 | (&composite->clk)->dev->name, parent_rate, divider->reg); |
| 43 | prediv_value = readl(divider->reg) >> divider->shift; |
| 44 | prediv_value &= clk_div_mask(divider->width); |
| 45 | |
| 46 | prediv_rate = divider_recalc_rate(clk, parent_rate, prediv_value, |
| 47 | NULL, divider->flags, |
| 48 | divider->width); |
| 49 | |
| 50 | div_value = readl(divider->reg) >> PCG_DIV_SHIFT; |
| 51 | div_value &= clk_div_mask(PCG_DIV_WIDTH); |
| 52 | |
| 53 | return divider_recalc_rate(clk, prediv_rate, div_value, NULL, |
| 54 | divider->flags, PCG_DIV_WIDTH); |
| 55 | } |
| 56 | |
| 57 | static int imx8m_clk_composite_compute_dividers(unsigned long rate, |
| 58 | unsigned long parent_rate, |
| 59 | int *prediv, int *postdiv) |
| 60 | { |
| 61 | int div1, div2; |
| 62 | int error = INT_MAX; |
| 63 | int ret = -EINVAL; |
| 64 | |
| 65 | *prediv = 1; |
| 66 | *postdiv = 1; |
| 67 | |
| 68 | for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) { |
| 69 | for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) { |
| 70 | int new_error = ((parent_rate / div1) / div2) - rate; |
| 71 | |
| 72 | if (abs(new_error) < abs(error)) { |
| 73 | *prediv = div1; |
| 74 | *postdiv = div2; |
| 75 | error = new_error; |
| 76 | ret = 0; |
| 77 | } |
| 78 | } |
| 79 | } |
| 80 | return ret; |
| 81 | } |
| 82 | |
| 83 | /* |
| 84 | * The clk are bound to a dev, because it is part of composite clk |
| 85 | * use composite clk to get dev |
| 86 | */ |
| 87 | static ulong imx8m_clk_composite_divider_set_rate(struct clk *clk, |
| 88 | unsigned long rate) |
| 89 | { |
| 90 | struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk); |
| 91 | struct clk_composite *composite = (struct clk_composite *)clk->data; |
| 92 | ulong parent_rate = clk_get_parent_rate(&composite->clk); |
| 93 | int prediv_value; |
| 94 | int div_value; |
| 95 | int ret; |
| 96 | u32 val; |
| 97 | |
| 98 | ret = imx8m_clk_composite_compute_dividers(rate, parent_rate, |
| 99 | &prediv_value, &div_value); |
| 100 | if (ret) |
| 101 | return ret; |
| 102 | |
| 103 | val = readl(divider->reg); |
| 104 | val &= ~((clk_div_mask(divider->width) << divider->shift) | |
| 105 | (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); |
| 106 | |
| 107 | val |= (u32)(prediv_value - 1) << divider->shift; |
| 108 | val |= (u32)(div_value - 1) << PCG_DIV_SHIFT; |
| 109 | writel(val, divider->reg); |
| 110 | |
| 111 | return clk_get_rate(&composite->clk); |
| 112 | } |
| 113 | |
| 114 | static const struct clk_ops imx8m_clk_composite_divider_ops = { |
| 115 | .get_rate = imx8m_clk_composite_divider_recalc_rate, |
| 116 | .set_rate = imx8m_clk_composite_divider_set_rate, |
| 117 | }; |
| 118 | |
| 119 | struct clk *imx8m_clk_composite_flags(const char *name, |
| 120 | const char * const *parent_names, |
| 121 | int num_parents, void __iomem *reg, |
| 122 | unsigned long flags) |
| 123 | { |
| 124 | struct clk *clk = ERR_PTR(-ENOMEM); |
| 125 | struct clk_divider *div = NULL; |
| 126 | struct clk_gate *gate = NULL; |
| 127 | struct clk_mux *mux = NULL; |
| 128 | |
| 129 | mux = kzalloc(sizeof(*mux), GFP_KERNEL); |
| 130 | if (!mux) |
| 131 | goto fail; |
| 132 | |
| 133 | mux->reg = reg; |
| 134 | mux->shift = PCG_PCS_SHIFT; |
| 135 | mux->mask = PCG_PCS_MASK; |
| 136 | mux->num_parents = num_parents; |
| 137 | mux->flags = flags; |
| 138 | mux->parent_names = parent_names; |
| 139 | |
| 140 | div = kzalloc(sizeof(*div), GFP_KERNEL); |
| 141 | if (!div) |
| 142 | goto fail; |
| 143 | |
| 144 | div->reg = reg; |
| 145 | div->shift = PCG_PREDIV_SHIFT; |
| 146 | div->width = PCG_PREDIV_WIDTH; |
| 147 | div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags; |
| 148 | |
| 149 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); |
| 150 | if (!gate) |
| 151 | goto fail; |
| 152 | |
| 153 | gate->reg = reg; |
| 154 | gate->bit_idx = PCG_CGC_SHIFT; |
| 155 | gate->flags = flags; |
| 156 | |
| 157 | clk = clk_register_composite(NULL, name, |
| 158 | parent_names, num_parents, |
| 159 | &mux->clk, &clk_mux_ops, &div->clk, |
| 160 | &imx8m_clk_composite_divider_ops, |
| 161 | &gate->clk, &clk_gate_ops, flags); |
| 162 | if (IS_ERR(clk)) |
| 163 | goto fail; |
| 164 | |
| 165 | return clk; |
| 166 | |
| 167 | fail: |
| 168 | kfree(gate); |
| 169 | kfree(div); |
| 170 | kfree(mux); |
| 171 | return ERR_CAST(clk); |
| 172 | } |