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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Frederik Kriewitz99396502009-08-23 12:56:42 +02002/*
3 * (C) Copyright 2004-2008
4 * Texas Instruments, <www.ti.com>
5 *
6 * Author :
7 * Sunil Kumar <sunilsaini05@gmail.com>
8 * Shashi Ranjan <shashiranjanmca05@gmail.com>
9 *
10 * (C) Copyright 2009
11 * Frederik Kriewitz <frederik@kriewitz.eu>
12 *
13 * Derived from Beagle Board and 3430 SDP code by
14 * Richard Woodruff <r-woodruff2@ti.com>
15 * Syed Mohammed Khasim <khasim@ti.com>
16 *
Frederik Kriewitz99396502009-08-23 12:56:42 +020017 */
Tom Rinied329b12024-04-30 20:43:03 -060018#include <config.h>
Anthoine Bourgeoiscf84a822015-01-02 00:35:43 +010019#include <dm.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060020#include <env.h>
Simon Glass97589732020-05-10 11:40:02 -060021#include <init.h>
Simon Glass9bc15642020-02-03 07:36:16 -070022#include <malloc.h>
Anthoine Bourgeoiscf84a822015-01-02 00:35:43 +010023#include <ns16550.h>
Frederik Kriewitz99396502009-08-23 12:56:42 +020024#include <twl4030.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060025#include <asm/global_data.h>
Frederik Kriewitz99396502009-08-23 12:56:42 +020026#include <asm/io.h>
Tom Rinibde8eea2011-09-03 21:52:45 -040027#include <asm/arch/mmc_host_def.h>
Frederik Kriewitz99396502009-08-23 12:56:42 +020028#include <asm/arch/mux.h>
29#include <asm/arch/sys_proto.h>
30#include <asm/arch/mem.h>
31#include <asm/mach-types.h>
32#include "devkit8000.h"
Simon Schwarzbbb57cb2012-03-15 04:01:40 +000033#include <asm/gpio.h>
Frederik Kriewitz99396502009-08-23 12:56:42 +020034#ifdef CONFIG_DRIVER_DM9000
35#include <net.h>
36#include <netdev.h>
37#endif
38
39DECLARE_GLOBAL_DATA_PTR;
40
Thomas Weber30e219a2011-12-13 05:54:17 +000041static u32 gpmc_net_config[GPMC_MAX_REG] = {
42 NET_GPMC_CONFIG1,
43 NET_GPMC_CONFIG2,
44 NET_GPMC_CONFIG3,
45 NET_GPMC_CONFIG4,
46 NET_GPMC_CONFIG5,
47 NET_GPMC_CONFIG6,
48 0
49};
50
Simon Glassb75b15b2020-12-03 16:55:23 -070051static const struct ns16550_plat devkit8000_serial = {
Adam Fordd1e22fa2016-03-07 21:08:49 -060052 .base = OMAP34XX_UART3,
53 .reg_shift = 2,
Heiko Schocher06f108e2017-01-18 08:05:49 +010054 .clock = V_NS16550_CLK,
55 .fcr = UART_FCR_DEFVAL,
Anthoine Bourgeoiscf84a822015-01-02 00:35:43 +010056};
57
Simon Glass1d8364a2020-12-28 20:34:54 -070058U_BOOT_DRVINFO(devkit8000_uart) = {
Thomas Chou52ac4432015-11-19 21:48:12 +080059 "ns16550_serial",
Anthoine Bourgeoiscf84a822015-01-02 00:35:43 +010060 &devkit8000_serial
61};
62
Frederik Kriewitz99396502009-08-23 12:56:42 +020063/*
64 * Routine: board_init
65 * Description: Early hardware init.
66 */
67int board_init(void)
68{
69 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
70 /* board id for Linux */
71 gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000;
72 /* boot param addr */
73 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
74
75 return 0;
76}
77
Simon Schwarz23cced12012-03-15 04:01:37 +000078/* Configure GPMC registers for DM9000 */
Tom Rini599b11b2022-12-02 16:42:18 -050079#define DM9000_BASE 0x2c000000
Simon Schwarz23cced12012-03-15 04:01:37 +000080static void gpmc_dm9000_config(void)
81{
82 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
Tom Rini599b11b2022-12-02 16:42:18 -050083 DM9000_BASE, GPMC_SIZE_16M);
Simon Schwarz23cced12012-03-15 04:01:37 +000084}
85
Frederik Kriewitz99396502009-08-23 12:56:42 +020086/*
87 * Routine: misc_init_r
88 * Description: Configure board specific parts
89 */
90int misc_init_r(void)
91{
92 struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
93#ifdef CONFIG_DRIVER_DM9000
94 uchar enetaddr[6];
95 u32 die_id_0;
96#endif
97
98 twl4030_power_init();
99#ifdef CONFIG_TWL4030_LED
Grazvydas Ignotas17887bf2009-12-10 17:10:21 +0200100 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
Frederik Kriewitz99396502009-08-23 12:56:42 +0200101#endif
102
103#ifdef CONFIG_DRIVER_DM9000
Tom Rini599b11b2022-12-02 16:42:18 -0500104 gpmc_dm9000_config();
Frederik Kriewitz99396502009-08-23 12:56:42 +0200105
106 /* Use OMAP DIE_ID as MAC address */
Simon Glass399a9ce2017-08-03 12:22:14 -0600107 if (!eth_env_get_enetaddr("ethaddr", enetaddr)) {
Frederik Kriewitz99396502009-08-23 12:56:42 +0200108 printf("ethaddr not set, using Die ID\n");
109 die_id_0 = readl(&id_base->die_id_0);
110 enetaddr[0] = 0x02; /* locally administered */
111 enetaddr[1] = readl(&id_base->die_id_1) & 0xff;
112 enetaddr[2] = (die_id_0 & 0xff000000) >> 24;
113 enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16;
114 enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8;
115 enetaddr[5] = (die_id_0 & 0x000000ff);
Simon Glass8551d552017-08-03 12:22:11 -0600116 eth_env_set_enetaddr("ethaddr", enetaddr);
Frederik Kriewitz99396502009-08-23 12:56:42 +0200117 }
118#endif
119
Paul Kocialkowski6bc318e2015-08-27 19:37:13 +0200120 omap_die_id_display();
Frederik Kriewitz99396502009-08-23 12:56:42 +0200121
122 return 0;
123}
124
125/*
126 * Routine: set_muxconf_regs
127 * Description: Setting up the configuration Mux registers specific to the
128 * hardware. Many pins need to be moved from protect to primary
129 * mode.
130 */
131void set_muxconf_regs(void)
132{
133 MUX_DEVKIT8000();
134}
135
Masahiro Yamada0a780172017-05-09 20:31:39 +0900136#if defined(CONFIG_MMC)
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900137int board_mmc_init(struct bd_info *bis)
Tom Rinibde8eea2011-09-03 21:52:45 -0400138{
Nikita Kiryanov4be9dbc2012-12-03 02:19:47 +0000139 return omap_mmc_init(0, 0, 0, -1, -1);
Tom Rinibde8eea2011-09-03 21:52:45 -0400140}
141#endif
142
Masahiro Yamada0a780172017-05-09 20:31:39 +0900143#if defined(CONFIG_MMC)
Paul Kocialkowski69559892014-11-08 20:55:47 +0100144void board_mmc_power_init(void)
145{
146 twl4030_power_mmc_init(0);
147}
148#endif
149
Simon Schwarz7ae359c2011-09-14 15:32:17 -0400150#if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
Frederik Kriewitz99396502009-08-23 12:56:42 +0200151/*
152 * Routine: board_eth_init
153 * Description: Setting up the Ethernet hardware.
154 */
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900155int board_eth_init(struct bd_info *bis)
Frederik Kriewitz99396502009-08-23 12:56:42 +0200156{
157 return dm9000_initialize(bis);
158}
159#endif
Tom Rini05800b92011-11-18 12:48:06 +0000160
Simon Schwarz23cced12012-03-15 04:01:37 +0000161#ifdef CONFIG_SPL_OS_BOOT
162/*
Robert P. J. Dayc5b1e5d2016-09-07 14:27:59 -0400163 * Do board specific preparation before SPL
Simon Schwarz23cced12012-03-15 04:01:37 +0000164 * Linux boot
165 */
166void spl_board_prepare_for_linux(void)
167{
168 gpmc_dm9000_config();
169}
170
Simon Schwarzbbb57cb2012-03-15 04:01:40 +0000171/*
172 * devkit8000 specific implementation of spl_start_uboot()
173 *
174 * RETURN
175 * 0 if the button is not pressed
176 * 1 if the button is pressed
177 */
178int spl_start_uboot(void)
179{
180 int val = 0;
Stefano Babicf51b4c72013-02-23 00:53:26 +0000181 if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
182 gpio_direction_input(SPL_OS_BOOT_KEY);
183 val = gpio_get_value(SPL_OS_BOOT_KEY);
184 gpio_free(SPL_OS_BOOT_KEY);
Simon Schwarzbbb57cb2012-03-15 04:01:40 +0000185 }
186 return !val;
187}
Simon Schwarz23cced12012-03-15 04:01:37 +0000188#endif
189
Tom Rini05800b92011-11-18 12:48:06 +0000190/*
191 * Routine: get_board_mem_timings
192 * Description: If we use SPL then there is no x-loader nor config header
193 * so we have to setup the DDR timings ourself on the first bank. This
194 * provides the timing values back to the function that configures
195 * the memory. We have either one or two banks of 128MB DDR.
196 */
Peter Baradaedb5c2f2012-11-13 07:40:28 +0000197void get_board_mem_timings(struct board_sdrc_timings *timings)
Tom Rini05800b92011-11-18 12:48:06 +0000198{
199 /* General SDRC config */
Peter Baradaedb5c2f2012-11-13 07:40:28 +0000200 timings->mcfg = MICRON_V_MCFG_165(128 << 20);
201 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
Tom Rini05800b92011-11-18 12:48:06 +0000202
203 /* AC timings */
Peter Baradaedb5c2f2012-11-13 07:40:28 +0000204 timings->ctrla = MICRON_V_ACTIMA_165;
205 timings->ctrlb = MICRON_V_ACTIMB_165;
Tom Rini05800b92011-11-18 12:48:06 +0000206
Peter Baradaedb5c2f2012-11-13 07:40:28 +0000207 timings->mr = MICRON_V_MR_165;
Tom Rini05800b92011-11-18 12:48:06 +0000208}