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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
York Sun46571362013-03-25 07:40:06 +00002/*
3 * Copyright 2012 Freescale Semiconductor, Inc.
York Sun46571362013-03-25 07:40:06 +00004 */
5
Tom Rinidee15a92024-04-30 20:40:48 -06006#include <linux/kernel.h>
York Sun46571362013-03-25 07:40:06 +00007#include <asm/fsl_serdes.h>
8#include <asm/processor.h>
9#include <asm/io.h>
Tom Rinidee15a92024-04-30 20:40:48 -060010#include <asm/ppc.h>
York Sun46571362013-03-25 07:40:06 +000011
Prabhakar Kushwaha3e5ce1c2014-01-24 17:51:50 +053012
13static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
14 [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
15 PCIE2, PCIE2, PCIE2, PCIE2},
16 [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
17 PCIE2, PCIE3, PCIE4, SATA1},
18 [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
19 PCIE2, PCIE3, SATA2, SATA1},
20 [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
21 PCIE2, PCIE2, PCIE2, PCIE2},
22 [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
23 PCIE2, PCIE2, PCIE2, PCIE2},
York Sun46571362013-03-25 07:40:06 +000024 [0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
25 PCIE2, PCIE3, PCIE4, SATA1},
26 [0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
27 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
Prabhakar Kushwaha3e5ce1c2014-01-24 17:51:50 +053028 [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
29 PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
York Sun46571362013-03-25 07:40:06 +000030 [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
31 PCIE2, PCIE3, PCIE4, SATA1},
Prabhakar Kushwaha3e5ce1c2014-01-24 17:51:50 +053032 [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
33 PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
York Sun46571362013-03-25 07:40:06 +000034 [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
35 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
Codrin Ciubotariud3904782015-01-12 14:08:31 +020036 [0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
37 PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},
38 [0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
39 PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5},
York Sun46571362013-03-25 07:40:06 +000040 [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
41 AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
York Sun46571362013-03-25 07:40:06 +000042 [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
43 PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
Prabhakar Kushwaha3e5ce1c2014-01-24 17:51:50 +053044 [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
45 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
46 [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
47 PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
York Sun46571362013-03-25 07:40:06 +000048};
49
York Sun46571362013-03-25 07:40:06 +000050enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
51{
Prabhakar Kushwaha3e5ce1c2014-01-24 17:51:50 +053052 return serdes_cfg_tbl[cfg][lane];
York Sun46571362013-03-25 07:40:06 +000053}
54
55int is_serdes_prtcl_valid(int serdes, u32 prtcl)
56{
57 int i;
58
Prabhakar Kushwaha3e5ce1c2014-01-24 17:51:50 +053059 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
York Sun46571362013-03-25 07:40:06 +000060 return 0;
61
62 for (i = 0; i < SRDS_MAX_LANES; i++) {
Prabhakar Kushwaha3e5ce1c2014-01-24 17:51:50 +053063 if (serdes_cfg_tbl[prtcl][i] != NONE)
York Sun46571362013-03-25 07:40:06 +000064 return 1;
65 }
66
67 return 0;
68}