| Mikhail Kalashnikov | cfce8e4 | 2023-06-07 01:07:45 +0100 | [diff] [blame] | 1 | /* |
| 2 | * sun50i H616 LPDDR3 timings, as programmed by Allwinner's boot0 |
| 3 | * |
| 4 | * The chips are probably able to be driven by a faster clock, but boot0 |
| 5 | * uses a more conservative timing (as usual). |
| 6 | * |
| 7 | * (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net> |
| 8 | * Based on H6 DDR3 timings: |
| 9 | * (C) Copyright 2018,2019 Arm Ltd. |
| 10 | * |
| 11 | * SPDX-License-Identifier: GPL-2.0+ |
| 12 | */ |
| 13 | |
| Mikhail Kalashnikov | cfce8e4 | 2023-06-07 01:07:45 +0100 | [diff] [blame] | 14 | #include <asm/arch/dram.h> |
| 15 | #include <asm/arch/cpu.h> |
| 16 | |
| 17 | void mctl_set_timing_params(const struct dram_para *para) |
| 18 | { |
| 19 | struct sunxi_mctl_ctl_reg * const mctl_ctl = |
| 20 | (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; |
| 21 | |
| 22 | u8 tccd = 2; |
| 23 | u8 tfaw = ns_to_t(50); |
| 24 | u8 trrd = max(ns_to_t(6), 4); |
| 25 | u8 trcd = ns_to_t(24); |
| 26 | u8 trc = ns_to_t(70); |
| 27 | u8 txp = max(ns_to_t(8), 3); |
| 28 | u8 trtp = max(ns_to_t(8), 2); |
| 29 | u8 trp = ns_to_t(27); |
| 30 | u8 tras = ns_to_t(41); |
| 31 | u16 trefi = ns_to_t(7800) / 64; |
| 32 | u16 trfc = ns_to_t(210); |
| 33 | u16 txsr = 88; |
| 34 | |
| 35 | u8 tmrw = 5; |
| 36 | u8 tmrd = 5; |
| 37 | u8 tmod = max(ns_to_t(15), 12); |
| 38 | u8 tcke = max(ns_to_t(6), 3); |
| 39 | u8 tcksrx = max(ns_to_t(12), 4); |
| 40 | u8 tcksre = max(ns_to_t(12), 4); |
| 41 | u8 tckesr = tcke + 2; |
| 42 | u8 trasmax = (para->clk / 2) / 16; |
| 43 | u8 txs = ns_to_t(360) / 32; |
| 44 | u8 txsdll = 16; |
| 45 | u8 txsabort = 4; |
| 46 | u8 txsfast = 4; |
| 47 | u8 tcl = 7; |
| 48 | u8 tcwl = 4; |
| 49 | u8 t_rdata_en = 12; |
| 50 | u8 t_wr_lat = 6; |
| 51 | |
| 52 | u8 twtp = 16; |
| 53 | u8 twr2rd = trtp + 9; |
| 54 | u8 trd2wr = 13; |
| 55 | |
| 56 | /* DRAM timing grabbed from tvbox with LPDDR3 memory */ |
| 57 | writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, |
| 58 | &mctl_ctl->dramtmg[0]); |
| 59 | writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]); |
| 60 | writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, |
| 61 | &mctl_ctl->dramtmg[2]); |
| 62 | writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]); |
| 63 | writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, |
| 64 | &mctl_ctl->dramtmg[4]); |
| 65 | writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, |
| 66 | &mctl_ctl->dramtmg[5]); |
| 67 | /* Value suggested by ZynqMP manual and used by libdram */ |
| 68 | writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]); |
| 69 | writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs, |
| 70 | &mctl_ctl->dramtmg[8]); |
| 71 | writel(0x00020208, &mctl_ctl->dramtmg[9]); |
| 72 | writel(0xE0C05, &mctl_ctl->dramtmg[10]); |
| 73 | writel(0x440C021C, &mctl_ctl->dramtmg[11]); |
| 74 | writel(8, &mctl_ctl->dramtmg[12]); |
| 75 | writel(0xA100002, &mctl_ctl->dramtmg[13]); |
| 76 | writel(txsr, &mctl_ctl->dramtmg[14]); |
| 77 | |
| 78 | writel(0x4f0112, &mctl_ctl->init[0]); |
| 79 | writel(0x420000, &mctl_ctl->init[1]); |
| 80 | writel(0xd05, &mctl_ctl->init[2]); |
| 81 | writel(0x83001c, &mctl_ctl->init[3]); |
| 82 | writel(0x00010000, &mctl_ctl->init[4]); |
| 83 | |
| 84 | writel(0, &mctl_ctl->dfimisc); |
| 85 | clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); |
| 86 | |
| 87 | /* Configure DFI timing */ |
| 88 | writel(t_wr_lat | 0x2000000 | (t_rdata_en << 16) | 0x808000, |
| 89 | &mctl_ctl->dfitmg0); |
| 90 | writel(0x100202, &mctl_ctl->dfitmg1); |
| 91 | |
| 92 | /* set refresh timing */ |
| 93 | writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg); |
| 94 | } |