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git01.mediatek.com / filogic / uboot / d4b57ec1d154916492fefd33ded0b3c2a7daff00 / . / arch / arm / mach-socfpga / mmu-arm64_s10.c
blob: b8e40d9a78893641d08997e2e7edb9a8f2263611 [file] [log] [blame]
Ley Foon Tanca6afad2018-05-24 00:17:26 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
Jit Loon Lim977071e2024-03-12 22:01:03 +0800[diff] [blame]3 * Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
Ley Foon Tanca6afad2018-05-24 00:17:26 +0800[diff] [blame]4 *
5 */
6
Ley Foon Tanca6afad2018-05-24 00:17:26 +0800[diff] [blame]7#include <asm/armv8/mmu.h>
Simon Glass3ba929a2020-10-30 21:38:53 -0600[diff] [blame]8#include <asm/global_data.h>
Ley Foon Tanca6afad2018-05-24 00:17:26 +0800[diff] [blame]9
10DECLARE_GLOBAL_DATA_PTR;
11
Jit Loon Lim977071e2024-03-12 22:01:03 +0800[diff] [blame]12#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
13static struct mm_region socfpga_agilex5_mem_map[] = {
14 {
15 /* OCRAM 512KB */
16 .virt = 0x00000000UL,
17 .phys = 0x00000000UL,
18 .size = 0x00080000UL,
19 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
20 PTE_BLOCK_NON_SHARE,
21 }, {
22 /* DEVICE */
23 .virt = 0x10808000UL,
24 .phys = 0x10808000UL,
25 .size = 0x0F7F8000UL,
26 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
27 PTE_BLOCK_NON_SHARE |
28 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
29 }, {
30 /* FPGA 1.5GB */
31 .virt = 0x20000000UL,
32 .phys = 0x20000000UL,
33 .size = 0x60000000UL,
34 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
35 PTE_BLOCK_NON_SHARE |
36 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
37 }, {
38 /* FPGA 15GB */
39 .virt = 0x440000000UL,
40 .phys = 0x440000000UL,
41 .size = 0x3C0000000UL,
42 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
43 PTE_BLOCK_NON_SHARE |
44 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
45 }, {
46 /* FPGA 240GB */
47 .virt = 0x4400000000UL,
48 .phys = 0x4400000000UL,
49 .size = 0x3C00000000UL,
50 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
51 PTE_BLOCK_NON_SHARE |
52 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
53 }, {
54 /* MEM 2GB */
55 .virt = 0x80000000UL,
56 .phys = 0x80000000UL,
57 .size = 0x80000000UL,
58 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
59 PTE_BLOCK_INNER_SHARE,
60 }, {
61 /* List terminator */
62 },
63};
64
65struct mm_region *mem_map = socfpga_agilex5_mem_map;
66
67#else
Ley Foon Tanca6afad2018-05-24 00:17:26 +0800[diff] [blame]68static struct mm_region socfpga_stratix10_mem_map[] = {
69 {
70 /* MEM 2GB*/
71 .virt = 0x0UL,
72 .phys = 0x0UL,
73 .size = 0x80000000UL,
74 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
75 PTE_BLOCK_INNER_SHARE,
76 }, {
77 /* FPGA 1.5GB */
78 .virt = 0x80000000UL,
79 .phys = 0x80000000UL,
80 .size = 0x60000000UL,
81 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
82 PTE_BLOCK_NON_SHARE |
83 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
84 }, {
85 /* DEVICE 142MB */
86 .virt = 0xF7000000UL,
87 .phys = 0xF7000000UL,
88 .size = 0x08E00000UL,
89 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
90 PTE_BLOCK_NON_SHARE |
91 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
92 }, {
93 /* OCRAM 1MB but available 256KB */
94 .virt = 0xFFE00000UL,
95 .phys = 0xFFE00000UL,
96 .size = 0x00100000UL,
97 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
98 PTE_BLOCK_INNER_SHARE,
99 }, {
100 /* DEVICE 32KB */
101 .virt = 0xFFFC0000UL,
102 .phys = 0xFFFC0000UL,
103 .size = 0x00008000UL,
104 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
105 PTE_BLOCK_NON_SHARE |
106 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
107 }, {
108 /* MEM 124GB */
109 .virt = 0x0100000000UL,
110 .phys = 0x0100000000UL,
111 .size = 0x1F00000000UL,
112 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
113 PTE_BLOCK_INNER_SHARE,
114 }, {
115 /* DEVICE 4GB */
116 .virt = 0x2000000000UL,
117 .phys = 0x2000000000UL,
118 .size = 0x0100000000UL,
119 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
120 PTE_BLOCK_NON_SHARE |
121 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
122 }, {
123 /* List terminator */
124 },
125};
126
127struct mm_region *mem_map = socfpga_stratix10_mem_map;
Jit Loon Lim977071e2024-03-12 22:01:03 +0800[diff] [blame]128#endif