Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 2 | /* |
Albert ARIBAUD | 340983d | 2011-04-22 19:41:02 +0200 | [diff] [blame] | 3 | * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 4 | * |
| 5 | * Based on original Kirkwood support which is |
| 6 | * Copyright (C) Marvell International Ltd. and its affiliates |
| 7 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 8 | */ |
| 9 | |
Tom Rini | f82559a | 2024-04-30 07:35:38 -0600 | [diff] [blame] | 10 | #include <config.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 11 | #include <init.h> |
Simon Glass | 495a5dc | 2019-11-14 12:57:30 -0700 | [diff] [blame] | 12 | #include <time.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 13 | #include <asm/global_data.h> |
Lei Wen | 749941a | 2011-10-24 16:27:32 +0000 | [diff] [blame] | 14 | #include <asm/io.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 15 | #include <linux/delay.h> |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 16 | |
| 17 | #define UBOOT_CNTR 0 /* counter to use for uboot timer */ |
| 18 | |
| 19 | /* Timer reload and current value registers */ |
| 20 | struct orion5x_tmr_val { |
| 21 | u32 reload; /* Timer reload reg */ |
| 22 | u32 val; /* Timer value reg */ |
| 23 | }; |
| 24 | |
| 25 | /* Timer registers */ |
| 26 | struct orion5x_tmr_registers { |
| 27 | u32 ctrl; /* Timer control reg */ |
| 28 | u32 pad[3]; |
| 29 | struct orion5x_tmr_val tmr[2]; |
| 30 | u32 wdt_reload; |
| 31 | u32 wdt_val; |
| 32 | }; |
| 33 | |
| 34 | struct orion5x_tmr_registers *orion5x_tmr_regs = |
| 35 | (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE; |
| 36 | |
| 37 | /* |
| 38 | * ARM Timers Registers Map |
| 39 | */ |
| 40 | #define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl) |
| 41 | #define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload) |
| 42 | #define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val) |
| 43 | |
| 44 | /* |
| 45 | * ARM Timers Control Register |
| 46 | * CPU_TIMERS_CTRL_REG (CTCR) |
| 47 | */ |
| 48 | #define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) |
| 49 | #define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) |
| 50 | #define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) |
| 51 | #define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) |
| 52 | |
| 53 | #define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) |
| 54 | #define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1) |
| 55 | #define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) |
| 56 | #define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) |
| 57 | |
| 58 | /* |
| 59 | * ARM Timer\Watchdog Reload Register |
| 60 | * CNTMR_RELOAD_REG (TRR) |
| 61 | */ |
| 62 | #define TRG_ARM_TIMER_REL_OFFS 0 |
| 63 | #define TRG_ARM_TIMER_REL_MASK 0xffffffff |
| 64 | |
| 65 | /* |
| 66 | * ARM Timer\Watchdog Register |
| 67 | * CNTMR_VAL_REG (TVRG) |
| 68 | */ |
| 69 | #define TVR_ARM_TIMER_OFFS 0 |
| 70 | #define TVR_ARM_TIMER_MASK 0xffffffff |
| 71 | #define TVR_ARM_TIMER_MAX 0xffffffff |
Wolfgang Denk | 62fb2b4 | 2021-09-27 17:42:39 +0200 | [diff] [blame] | 72 | #define TIMER_LOAD_VAL 0xffffffff |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 73 | |
| 74 | static inline ulong read_timer(void) |
| 75 | { |
| 76 | return readl(CNTMR_VAL_REG(UBOOT_CNTR)) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 77 | / (CFG_SYS_TCLK / 1000); |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 78 | } |
| 79 | |
Heiko Schocher | 5504dab | 2011-01-20 22:56:39 +0000 | [diff] [blame] | 80 | DECLARE_GLOBAL_DATA_PTR; |
| 81 | |
Simon Glass | 2655ee1 | 2012-12-13 20:48:34 +0000 | [diff] [blame] | 82 | #define timestamp gd->arch.tbl |
Simon Glass | a848da5 | 2012-12-13 20:48:35 +0000 | [diff] [blame] | 83 | #define lastdec gd->arch.lastinc |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 84 | |
Patrick Delaunay | 9858a60 | 2018-10-05 11:33:52 +0200 | [diff] [blame] | 85 | static ulong get_timer_masked(void) |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 86 | { |
| 87 | ulong now = read_timer(); |
| 88 | |
| 89 | if (lastdec >= now) { |
| 90 | /* normal mode */ |
| 91 | timestamp += lastdec - now; |
| 92 | } else { |
| 93 | /* we have an overflow ... */ |
| 94 | timestamp += lastdec + |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 95 | (TIMER_LOAD_VAL / (CFG_SYS_TCLK / 1000)) - now; |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 96 | } |
| 97 | lastdec = now; |
| 98 | |
| 99 | return timestamp; |
| 100 | } |
| 101 | |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 102 | ulong get_timer(ulong base) |
| 103 | { |
| 104 | return get_timer_masked() - base; |
| 105 | } |
| 106 | |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 107 | static inline ulong uboot_cntr_val(void) |
| 108 | { |
| 109 | return readl(CNTMR_VAL_REG(UBOOT_CNTR)); |
| 110 | } |
| 111 | |
| 112 | void __udelay(unsigned long usec) |
| 113 | { |
| 114 | uint current; |
| 115 | ulong delayticks; |
| 116 | |
| 117 | current = uboot_cntr_val(); |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 118 | delayticks = (usec * (CFG_SYS_TCLK / 1000000)); |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 119 | |
| 120 | if (current < delayticks) { |
| 121 | delayticks -= current; |
| 122 | while (uboot_cntr_val() < current) |
| 123 | ; |
| 124 | while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val()) |
| 125 | ; |
| 126 | } else { |
| 127 | while (uboot_cntr_val() > (current - delayticks)) |
| 128 | ; |
| 129 | } |
| 130 | } |
| 131 | |
| 132 | /* |
| 133 | * init the counter |
| 134 | */ |
| 135 | int timer_init(void) |
| 136 | { |
| 137 | unsigned int cntmrctrl; |
| 138 | |
| 139 | /* load value into timer */ |
| 140 | writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); |
| 141 | writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); |
| 142 | |
| 143 | /* enable timer in auto reload mode */ |
| 144 | cntmrctrl = readl(CNTMR_CTRL_REG); |
| 145 | cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR); |
| 146 | cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); |
| 147 | writel(cntmrctrl, CNTMR_CTRL_REG); |
Albert Aribaud | fd5f973 | 2010-09-23 21:49:23 +0200 | [diff] [blame] | 148 | return 0; |
| 149 | } |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 150 | |
Albert Aribaud | fd5f973 | 2010-09-23 21:49:23 +0200 | [diff] [blame] | 151 | void timer_init_r(void) |
| 152 | { |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 153 | /* init the timestamp and lastdec value */ |
Graeme Russ | 944a7fe | 2011-07-15 02:21:14 +0000 | [diff] [blame] | 154 | lastdec = read_timer(); |
| 155 | timestamp = 0; |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 156 | } |
Prafulla Wadaskar | f4ce6ad | 2012-02-08 14:15:53 +0530 | [diff] [blame] | 157 | |
| 158 | /* |
| 159 | * This function is derived from PowerPC code (read timebase as long long). |
| 160 | * On ARM it just returns the timer value. |
| 161 | */ |
| 162 | unsigned long long get_ticks(void) |
| 163 | { |
| 164 | return get_timer(0); |
| 165 | } |
| 166 | |
| 167 | /* |
| 168 | * This function is derived from PowerPC code (timebase clock frequency). |
| 169 | * On ARM it returns the number of timer ticks per second. |
| 170 | */ |
Simon Glass | a9dc068 | 2019-12-28 10:44:59 -0700 | [diff] [blame] | 171 | ulong get_tbclk(void) |
Prafulla Wadaskar | f4ce6ad | 2012-02-08 14:15:53 +0530 | [diff] [blame] | 172 | { |
| 173 | return (ulong)CONFIG_SYS_HZ; |
| 174 | } |