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git01.mediatek.com / filogic / uboot / d4b57ec1d154916492fefd33ded0b3c2a7daff00 / . / arch / arm / mach-imx / mx7 / ddr.c
blob: c4a90be3945b5d55859d6f6bf429192c995f2dc3 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Uri Mashiachdd587fa2017-09-24 09:00:23 +0300[diff] [blame]2/*
3 * DDR controller configuration for the i.MX7 architecture
4 *
5 * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
6 *
7 * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
Uri Mashiachdd587fa2017-09-24 09:00:23 +0300[diff] [blame]8 */
9
10#include <linux/types.h>
11#include <asm/io.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/crm_regs.h>
14#include <asm/arch/mx7-ddr.h>
Marek Vasutf4bb5652020-05-30 02:14:48 +0200[diff] [blame]15#include <linux/delay.h>
Uri Mashiachdd587fa2017-09-24 09:00:23 +0300[diff] [blame]16
17/*
18 * Routine: mx7_dram_cfg
19 * Description: DDR controller configuration
20 *
21 * @ddrc_regs_val: DDRC registers value
22 * @ddrc_mp_val: DDRC_MP registers value
23 * @ddr_phy_regs_val: DDR_PHY registers value
24 * @calib_param: calibration parameters
25 *
26 */
27void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
28 struct ddr_phy *ddr_phy_regs_val,
29 struct mx7_calibration *calib_param)
30{
31 struct src *const src_regs = (struct src *)SRC_BASE_ADDR;
32 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
33 struct ddrc_mp *const ddrc_mp_reg = (struct ddrc_mp *)DDRC_MP_BASE_ADDR;
34 struct ddr_phy *const ddr_phy_regs =
35 (struct ddr_phy *)DDRPHY_IPS_BASE_ADDR;
36 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs =
37 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
38 int i;
39
Marek Vasutf4bb5652020-05-30 02:14:48 +0200[diff] [blame]40 /*
41 * iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power
42 * row 2 says "Reset controller / PHY by driving core_ddrc_rst = 0 ,
43 * aresetn_n = 0, presetn = 0. That means reset everything.
44 */
45 writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK | SRC_DDRC_RCR_DDRC_PRST_MASK,
46 &src_regs->ddrc_rcr);
47
48 /*
49 * iMX7D RM 6.2.7.26 SRC_DDRC_RCR says wait 30 cycles (of unknown).
50 * If we assume this is 30 cycles at 100 MHz (about the rate of a
51 * DRAM bus), that's 300 nS, so waiting 10 uS is more then plenty.
52 */
53 udelay(10);
54
55 /* De-assert DDR Controller 'preset' and DDR PHY reset */
56 clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_PRST_MASK);
Uri Mashiachdd587fa2017-09-24 09:00:23 +0300[diff] [blame]57
58 /* DDR controller configuration */
59 writel(ddrc_regs_val->mstr, &ddrc_regs->mstr);
60 writel(ddrc_regs_val->rfshtmg, &ddrc_regs->rfshtmg);
61 writel(ddrc_mp_val->pctrl_0, &ddrc_mp_reg->pctrl_0);
62 writel(ddrc_regs_val->init1, &ddrc_regs->init1);
63 writel(ddrc_regs_val->init0, &ddrc_regs->init0);
64 writel(ddrc_regs_val->init3, &ddrc_regs->init3);
65 writel(ddrc_regs_val->init4, &ddrc_regs->init4);
66 writel(ddrc_regs_val->init5, &ddrc_regs->init5);
67 writel(ddrc_regs_val->rankctl, &ddrc_regs->rankctl);
68 writel(ddrc_regs_val->dramtmg0, &ddrc_regs->dramtmg0);
69 writel(ddrc_regs_val->dramtmg1, &ddrc_regs->dramtmg1);
70 writel(ddrc_regs_val->dramtmg2, &ddrc_regs->dramtmg2);
71 writel(ddrc_regs_val->dramtmg3, &ddrc_regs->dramtmg3);
72 writel(ddrc_regs_val->dramtmg4, &ddrc_regs->dramtmg4);
73 writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5);
74 writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8);
75 writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0);
Marek Vasut494c4d82020-05-22 01:12:39 +0200[diff] [blame]76 writel(ddrc_regs_val->zqctl1, &ddrc_regs->zqctl1);
Uri Mashiachdd587fa2017-09-24 09:00:23 +0300[diff] [blame]77 writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0);
78 writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1);
79 writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0);
80 writel(ddrc_regs_val->dfiupd1, &ddrc_regs->dfiupd1);
81 writel(ddrc_regs_val->dfiupd2, &ddrc_regs->dfiupd2);
82 writel(ddrc_regs_val->addrmap0, &ddrc_regs->addrmap0);
83 writel(ddrc_regs_val->addrmap1, &ddrc_regs->addrmap1);
84 writel(ddrc_regs_val->addrmap4, &ddrc_regs->addrmap4);
85 writel(ddrc_regs_val->addrmap5, &ddrc_regs->addrmap5);
86 writel(ddrc_regs_val->addrmap6, &ddrc_regs->addrmap6);
87 writel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg);
88 writel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap);
89
Marek Vasutf4bb5652020-05-30 02:14:48 +0200[diff] [blame]90 /* De-assert DDR Controller 'core_ddrc_rstn' and 'aresetn' */
Uri Mashiachdd587fa2017-09-24 09:00:23 +0300[diff] [blame]91 clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK);
92
93 /* PHY configuration */
94 writel(ddr_phy_regs_val->phy_con0, &ddr_phy_regs->phy_con0);
95 writel(ddr_phy_regs_val->phy_con1, &ddr_phy_regs->phy_con1);
96 writel(ddr_phy_regs_val->phy_con4, &ddr_phy_regs->phy_con4);
97 writel(ddr_phy_regs_val->mdll_con0, &ddr_phy_regs->mdll_con0);
98 writel(ddr_phy_regs_val->drvds_con0, &ddr_phy_regs->drvds_con0);
99 writel(ddr_phy_regs_val->offset_wr_con0, &ddr_phy_regs->offset_wr_con0);
100 writel(ddr_phy_regs_val->offset_rd_con0, &ddr_phy_regs->offset_rd_con0);
101 writel(ddr_phy_regs_val->cmd_sdll_con0 |
102 DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
103 &ddr_phy_regs->cmd_sdll_con0);
104 writel(ddr_phy_regs_val->cmd_sdll_con0 &
105 ~DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
106 &ddr_phy_regs->cmd_sdll_con0);
107 writel(ddr_phy_regs_val->offset_lp_con0, &ddr_phy_regs->offset_lp_con0);
Marek Vasut6d2fa042020-08-05 15:30:43 +0200[diff] [blame]108 writel(ddr_phy_regs_val->cmd_deskew_con0,
109 &ddr_phy_regs->cmd_deskew_con0);
110 writel(ddr_phy_regs_val->cmd_deskew_con1,
111 &ddr_phy_regs->cmd_deskew_con1);
112 writel(ddr_phy_regs_val->cmd_deskew_con2,
113 &ddr_phy_regs->cmd_deskew_con2);
114 writel(ddr_phy_regs_val->cmd_deskew_con3,
115 &ddr_phy_regs->cmd_deskew_con3);
116 writel(ddr_phy_regs_val->cmd_lvl_con0, &ddr_phy_regs->cmd_lvl_con0);
Uri Mashiachdd587fa2017-09-24 09:00:23 +0300[diff] [blame]117
118 /* calibration */
119 for (i = 0; i < calib_param->num_val; i++)
120 writel(calib_param->values[i], &ddr_phy_regs->zq_con0);
121
122 /* Wake_up DDR PHY */
123 HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_N_N);
124 writel(IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(0xf) |
125 IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK,
126 &iomuxc_gpr_regs->gpr[8]);
127 HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_R_W);
128}
129
130/*
131 * Routine: imx_ddr_size
132 * Description: extract the current DRAM size from the DDRC registers
133 *
134 * @return: DRAM size
135 */
136unsigned int imx_ddr_size(void)
137{
138 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
139 u32 reg_val, field_val;
140 int bits = 0;/* Number of address bits */
141
142 /* Count data bus width bits */
143 reg_val = readl(&ddrc_regs->mstr);
144 field_val = (reg_val & MSTR_DATA_BUS_WIDTH_MASK) >> MSTR_DATA_BUS_WIDTH_SHIFT;
145 bits += 2 - field_val;
146 /* Count rank address bits */
147 field_val = (reg_val & MSTR_DATA_ACTIVE_RANKS_MASK) >> MSTR_DATA_ACTIVE_RANKS_SHIFT;
148 if (field_val > 1)
149 bits += field_val - 1;
150 /* Count column address bits */
151 bits += 2;/* Column address 0 and 1 are fixed mapped */
152 reg_val = readl(&ddrc_regs->addrmap2);
153 field_val = (reg_val & ADDRMAP2_COL_B2_MASK) >> ADDRMAP2_COL_B2_SHIFT;
154 if (field_val <= 7)
155 bits++;
156 field_val = (reg_val & ADDRMAP2_COL_B3_MASK) >> ADDRMAP2_COL_B3_SHIFT;
157 if (field_val <= 7)
158 bits++;
159 field_val = (reg_val & ADDRMAP2_COL_B4_MASK) >> ADDRMAP2_COL_B4_SHIFT;
160 if (field_val <= 7)
161 bits++;
162 field_val = (reg_val & ADDRMAP2_COL_B5_MASK) >> ADDRMAP2_COL_B5_SHIFT;
163 if (field_val <= 7)
164 bits++;
165 reg_val = readl(&ddrc_regs->addrmap3);
166 field_val = (reg_val & ADDRMAP3_COL_B6_MASK) >> ADDRMAP3_COL_B6_SHIFT;
167 if (field_val <= 7)
168 bits++;
169 field_val = (reg_val & ADDRMAP3_COL_B7_MASK) >> ADDRMAP3_COL_B7_SHIFT;
170 if (field_val <= 7)
171 bits++;
172 field_val = (reg_val & ADDRMAP3_COL_B8_MASK) >> ADDRMAP3_COL_B8_SHIFT;
173 if (field_val <= 7)
174 bits++;
175 field_val = (reg_val & ADDRMAP3_COL_B9_MASK) >> ADDRMAP3_COL_B9_SHIFT;
176 if (field_val <= 7)
177 bits++;
178 reg_val = readl(&ddrc_regs->addrmap4);
179 field_val = (reg_val & ADDRMAP4_COL_B10_MASK) >> ADDRMAP4_COL_B10_SHIFT;
180 if (field_val <= 7)
181 bits++;
182 field_val = (reg_val & ADDRMAP4_COL_B11_MASK) >> ADDRMAP4_COL_B11_SHIFT;
183 if (field_val <= 7)
184 bits++;
185 /* Count row address bits */
186 reg_val = readl(&ddrc_regs->addrmap5);
187 field_val = (reg_val & ADDRMAP5_ROW_B0_MASK) >> ADDRMAP5_ROW_B0_SHIFT;
188 if (field_val <= 11)
189 bits++;
190 field_val = (reg_val & ADDRMAP5_ROW_B1_MASK) >> ADDRMAP5_ROW_B1_SHIFT;
191 if (field_val <= 11)
192 bits++;
193 field_val = (reg_val & ADDRMAP5_ROW_B2_10_MASK) >> ADDRMAP5_ROW_B2_10_SHIFT;
194 if (field_val <= 11)
195 bits += 9;
196 field_val = (reg_val & ADDRMAP5_ROW_B11_MASK) >> ADDRMAP5_ROW_B11_SHIFT;
197 if (field_val <= 11)
198 bits++;
199 reg_val = readl(&ddrc_regs->addrmap6);
200 field_val = (reg_val & ADDRMAP6_ROW_B12_MASK) >> ADDRMAP6_ROW_B12_SHIFT;
201 if (field_val <= 11)
202 bits++;
203 field_val = (reg_val & ADDRMAP6_ROW_B13_MASK) >> ADDRMAP6_ROW_B13_SHIFT;
204 if (field_val <= 11)
205 bits++;
206 field_val = (reg_val & ADDRMAP6_ROW_B14_MASK) >> ADDRMAP6_ROW_B14_SHIFT;
207 if (field_val <= 11)
208 bits++;
209 field_val = (reg_val & ADDRMAP6_ROW_B15_MASK) >> ADDRMAP6_ROW_B15_SHIFT;
210 if (field_val <= 11)
211 bits++;
212 /* Count bank bits */
213 reg_val = readl(&ddrc_regs->addrmap1);
214 field_val = (reg_val & ADDRMAP1_BANK_B0_MASK) >> ADDRMAP1_BANK_B0_SHIFT;
215 if (field_val <= 30)
216 bits++;
217 field_val = (reg_val & ADDRMAP1_BANK_B1_MASK) >> ADDRMAP1_BANK_B1_SHIFT;
218 if (field_val <= 30)
219 bits++;
220 field_val = (reg_val & ADDRMAP1_BANK_B2_MASK) >> ADDRMAP1_BANK_B2_SHIFT;
221 if (field_val <= 29)
222 bits++;
223
Marcel Ziswiler21d69562018-09-19 13:01:55 +0200[diff] [blame]224 /* cap to max 2 GB */
225 if (bits > 31)
226 bits = 31;
227
Uri Mashiachdd587fa2017-09-24 09:00:23 +0300[diff] [blame]228 return 1 << bits;
229}