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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Hugo Villeneuve4e352ef2008-07-11 15:10:13 -04002/*
3 * Power and Sleep Controller (PSC) functions.
4 *
5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
7 * Copyright (C) 2004 Texas Instruments.
Hugo Villeneuve4e352ef2008-07-11 15:10:13 -04008 */
9
Hugo Villeneuve4e352ef2008-07-11 15:10:13 -040010#include <asm/arch/hardware.h>
Sekhar Nori302fc2f2009-11-12 11:07:22 -050011#include <asm/io.h>
Hugo Villeneuve4e352ef2008-07-11 15:10:13 -040012
13/*
David Brownell5f02add2009-05-15 23:44:08 +020014 * The PSC manages three inputs to a "module" which may be a peripheral or
15 * CPU. Those inputs are the module's: clock; reset signal; and sometimes
16 * its power domain. For our purposes, we only care whether clock and power
17 * are active, and the module is out of reset.
18 *
19 * DaVinci chips may include two separate power domains: "Always On" and "DSP".
20 * Chips without a DSP generally have only one domain.
21 *
22 * The "Always On" power domain is always on when the chip is on, and is
23 * powered by the VDD pins (on DM644X). The majority of DaVinci modules
24 * lie within the "Always On" power domain.
25 *
26 * A separate domain called the "DSP" domain houses the C64x+ and other video
27 * hardware such as VICP. In some chips, the "DSP" domain is not always on.
28 * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
Hugo Villeneuve4e352ef2008-07-11 15:10:13 -040029 */
30
31/* Works on Always On power domain only (no PD argument) */
Christian Riescha4cd16f2011-10-12 21:26:43 +000032static void lpsc_transition(unsigned int id, unsigned int state)
Hugo Villeneuve4e352ef2008-07-11 15:10:13 -040033{
Sekhar Nori302fc2f2009-11-12 11:07:22 -050034 dv_reg_p mdstat, mdctl, ptstat, ptcmd;
Sekhar Nori302fc2f2009-11-12 11:07:22 -050035 struct davinci_psc_regs *psc_regs;
Hugo Villeneuve4e352ef2008-07-11 15:10:13 -040036
Sekhar Nori302fc2f2009-11-12 11:07:22 -050037 if (id < DAVINCI_LPSC_PSC1_BASE) {
38 if (id >= PSC_PSC0_MODULE_ID_CNT)
39 return;
40 psc_regs = davinci_psc0_regs;
41 mdstat = &psc_regs->psc0.mdstat[id];
42 mdctl = &psc_regs->psc0.mdctl[id];
43 } else {
44 id -= DAVINCI_LPSC_PSC1_BASE;
45 if (id >= PSC_PSC1_MODULE_ID_CNT)
46 return;
47 psc_regs = davinci_psc1_regs;
48 mdstat = &psc_regs->psc1.mdstat[id];
49 mdctl = &psc_regs->psc1.mdctl[id];
50 }
51 ptstat = &psc_regs->ptstat;
52 ptcmd = &psc_regs->ptcmd;
Hugo Villeneuve4e352ef2008-07-11 15:10:13 -040053
Sekhar Nori302fc2f2009-11-12 11:07:22 -050054 while (readl(ptstat) & 0x01)
David Brownell5f02add2009-05-15 23:44:08 +020055 continue;
Hugo Villeneuve4e352ef2008-07-11 15:10:13 -040056
Christian Riescha4cd16f2011-10-12 21:26:43 +000057 if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
58 return; /* Already in that state */
Hugo Villeneuve4e352ef2008-07-11 15:10:13 -040059
Christian Riescha4cd16f2011-10-12 21:26:43 +000060 writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
Sekhar Nori302fc2f2009-11-12 11:07:22 -050061 writel(0x01, ptcmd);
Hugo Villeneuve4e352ef2008-07-11 15:10:13 -040062
Sekhar Nori302fc2f2009-11-12 11:07:22 -050063 while (readl(ptstat) & 0x01)
David Brownell5f02add2009-05-15 23:44:08 +020064 continue;
Christian Riescha4cd16f2011-10-12 21:26:43 +000065 while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
David Brownell5f02add2009-05-15 23:44:08 +020066 continue;
Hugo Villeneuve4e352ef2008-07-11 15:10:13 -040067}
68
Christian Riescha4cd16f2011-10-12 21:26:43 +000069void lpsc_on(unsigned int id)
70{
71 lpsc_transition(id, 0x03);
72}
73
74void lpsc_syncreset(unsigned int id)
75{
76 lpsc_transition(id, 0x01);
77}
78
Sughosh Ganu282e2af2012-08-09 10:45:20 +000079void lpsc_disable(unsigned int id)
80{
81 lpsc_transition(id, 0x0);
82}