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git01.mediatek.com / filogic / uboot / d4b57ec1d154916492fefd33ded0b3c2a7daff00 / . / arch / arm / mach-at91 / arm926ejs / reset.c
blob: 01b2663f96c9288395b14d0209ff332ac527b976 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Jean-Christophe PLAGNIOL-VILLARD9c5c8242009-05-31 12:44:45 +0200[diff] [blame]2/*
3 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +0100[diff] [blame]4 * Stelian Pop <stelian@popies.net>
Jean-Christophe PLAGNIOL-VILLARD9c5c8242009-05-31 12:44:45 +0200[diff] [blame]5 * Lead Tech Design <www.leadtechdesign.com>
Jean-Christophe PLAGNIOL-VILLARD9c5c8242009-05-31 12:44:45 +0200[diff] [blame]6 */
7
Simon Glassafb02152019-12-28 10:45:01 -0700[diff] [blame]8#include <cpu_func.h>
Reinhard Meyerb06208c2010-11-07 13:26:14 +0100[diff] [blame]9#include <asm/io.h>
Jean-Christophe PLAGNIOL-VILLARD9c5c8242009-05-31 12:44:45 +0200[diff] [blame]10#include <asm/arch/hardware.h>
11#include <asm/arch/at91_rstc.h>
Jean-Christophe PLAGNIOL-VILLARD9c5c8242009-05-31 12:44:45 +0200[diff] [blame]12
Reinhard Meyer609e6312010-08-09 13:25:37 +0200[diff] [blame]13/* Reset the cpu by telling the reset controller to do so */
Harald Seiler6f14d5f2020-12-15 16:47:52 +0100[diff] [blame]14void reset_cpu(void)
Jean-Christophe PLAGNIOL-VILLARD9c5c8242009-05-31 12:44:45 +0200[diff] [blame]15{
Reinhard Meyere260d0b2010-11-03 15:39:55 +0100[diff] [blame]16 at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
Jens Scharsiga4db1ca2010-02-03 22:46:58 +0100[diff] [blame]17
Reinhard Meyer609e6312010-08-09 13:25:37 +0200[diff] [blame]18 writel(AT91_RSTC_KEY
19 | AT91_RSTC_CR_PROCRST /* Processor Reset */
20 | AT91_RSTC_CR_PERRST /* Peripheral Reset */
21#ifdef CONFIG_AT91RESET_EXTRST
22 | AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */
23#endif
24 , &rstc->cr);
25 /* never reached */
26 while (1)
27 ;
Jean-Christophe PLAGNIOL-VILLARD9c5c8242009-05-31 12:44:45 +0200[diff] [blame]28}