Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / d4b57ec1d154916492fefd33ded0b3c2a7daff00 / . / arch / arm / lib / bootm-fdt.c
blob: 2671f9a0ebf5e71ac95214f374955c370497590a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Simon Glass653909f2013-05-08 08:06:03 +0000[diff] [blame]2/*
3 * Copyright (c) 2013, Google Inc.
4 *
5 * Copyright (C) 2011
6 * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
7 * - Added prep subcommand support
8 * - Reorganized source - modeled after powerpc version
9 *
10 * (C) Copyright 2002
11 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
12 * Marius Groeger <mgroeger@sysgo.de>
13 *
14 * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
Simon Glass653909f2013-05-08 08:06:03 +0000[diff] [blame]15 */
16
Simon Glass653909f2013-05-08 08:06:03 +0000[diff] [blame]17#include <fdt_support.h>
Tom Rini9fcb5ef2015-05-14 11:07:03 -0400[diff] [blame]18#ifdef CONFIG_ARMV7_NONSEC
Jan Kiszkacb334402015-04-21 07:18:32 +0200[diff] [blame]19#include <asm/armv7.h>
Tom Rini9fcb5ef2015-05-14 11:07:03 -0400[diff] [blame]20#endif
Simon Glass3ba929a2020-10-30 21:38:53 -0600[diff] [blame]21#include <asm/global_data.h>
Tom Rinifb02cc12015-03-05 20:19:36 -0500[diff] [blame]22#include <asm/psci.h>
Masahiro Yamada2663cd62016-06-27 19:31:05 +0900[diff] [blame]23#include <asm/spin_table.h>
Simon Glass653909f2013-05-08 08:06:03 +0000[diff] [blame]24
25DECLARE_GLOBAL_DATA_PTR;
26
Prabhakar Kushwahac10b9672017-11-23 16:51:41 +0530[diff] [blame]27#ifdef CONFIG_FMAN_ENET
28__weak int fdt_update_ethernet_dt(void *blob)
29{
30 return 0;
31}
32#endif
33
Ma Haijun62358242014-07-12 14:24:06 +0100[diff] [blame]34int arch_fixup_fdt(void *blob)
Simon Glass653909f2013-05-08 08:06:03 +0000[diff] [blame]35{
Heiko Schocher375cc6e2018-01-17 07:00:37 +0100[diff] [blame]36 __maybe_unused int ret = 0;
B, Ravi4d863562017-04-18 17:27:26 +0530[diff] [blame]37#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_OF_LIBFDT)
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900[diff] [blame]38 struct bd_info *bd = gd->bd;
B, Ravi4d863562017-04-18 17:27:26 +0530[diff] [blame]39 int bank;
Simon Glass653909f2013-05-08 08:06:03 +0000[diff] [blame]40 u64 start[CONFIG_NR_DRAM_BANKS];
41 u64 size[CONFIG_NR_DRAM_BANKS];
42
43 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
44 start[bank] = bd->bi_dram[bank].start;
45 size[bank] = bd->bi_dram[bank].size;
Jan Kiszkacb334402015-04-21 07:18:32 +0200[diff] [blame]46#ifdef CONFIG_ARMV7_NONSEC
47 ret = armv7_apply_memory_carveout(&start[bank], &size[bank]);
48 if (ret)
49 return ret;
50#endif
Simon Glass653909f2013-05-08 08:06:03 +0000[diff] [blame]51 }
52
B, Ravi4d863562017-04-18 17:27:26 +0530[diff] [blame]53#ifdef CONFIG_OF_LIBFDT
Marc Zyngierb32cf0e2014-07-12 14:24:07 +0100[diff] [blame]54 ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
Marc Zyngierb32cf0e2014-07-12 14:24:07 +0100[diff] [blame]55 if (ret)
56 return ret;
B, Ravi4d863562017-04-18 17:27:26 +0530[diff] [blame]57#endif
Marc Zyngierb32cf0e2014-07-12 14:24:07 +0100[diff] [blame]58
Masahiro Yamada2663cd62016-06-27 19:31:05 +0900[diff] [blame]59#ifdef CONFIG_ARMV8_SPIN_TABLE
60 ret = spin_table_update_dt(blob);
61 if (ret)
62 return ret;
63#endif
64
macro.wave.z@gmail.com05725ed2016-12-08 11:58:25 +0800[diff] [blame]65#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI) || \
Michael Walle16fd24c2020-11-18 17:45:54 +0100[diff] [blame]66 CONFIG_IS_ENABLED(SEC_FIRMWARE_ARMV8_PSCI)
Tom Rinifb02cc12015-03-05 20:19:36 -0500[diff] [blame]67 ret = psci_update_dt(blob);
Masahiro Yamada909cc1c2016-06-17 21:51:48 +0900[diff] [blame]68 if (ret)
69 return ret;
Marc Zyngierb32cf0e2014-07-12 14:24:07 +0100[diff] [blame]70#endif
B, Ravi4d863562017-04-18 17:27:26 +0530[diff] [blame]71#endif
Masahiro Yamada909cc1c2016-06-17 21:51:48 +0900[diff] [blame]72
Prabhakar Kushwahac10b9672017-11-23 16:51:41 +0530[diff] [blame]73#ifdef CONFIG_FMAN_ENET
74 ret = fdt_update_ethernet_dt(blob);
75 if (ret)
76 return ret;
77#endif
Masahiro Yamada909cc1c2016-06-17 21:51:48 +0900[diff] [blame]78 return 0;
Simon Glass653909f2013-05-08 08:06:03 +0000[diff] [blame]79}