Andre Przywara | b277429 | 2022-01-23 00:28:43 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> |
| 4 | * |
| 5 | * (C) Copyright 2007-2011 |
| 6 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> |
| 7 | * Tom Cubie <tangliang@allwinnertech.com> |
| 8 | * |
| 9 | * SRAM init for older sunxi SoCs. |
| 10 | */ |
| 11 | |
Andre Przywara | b277429 | 2022-01-23 00:28:43 +0000 | [diff] [blame] | 12 | #include <init.h> |
| 13 | #include <asm/io.h> |
Andre Przywara | e42015b | 2022-07-03 00:14:24 +0100 | [diff] [blame] | 14 | #include <asm/arch/cpu.h> |
Andre Przywara | b277429 | 2022-01-23 00:28:43 +0000 | [diff] [blame] | 15 | |
| 16 | void sunxi_sram_init(void) |
| 17 | { |
| 18 | /* |
| 19 | * Undocumented magic taken from boot0, without this DRAM |
| 20 | * access gets messed up (seems cache related). |
| 21 | * The boot0 sources describe this as: "config ema for cache sram" |
| 22 | * Newer SoCs (A83T, H3 and anything beyond) don't need this anymore. |
| 23 | */ |
| 24 | if (IS_ENABLED(CONFIG_MACH_SUN6I)) |
| 25 | setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); |
| 26 | |
| 27 | if (IS_ENABLED(CONFIG_MACH_SUN8I)) { |
| 28 | uint version = sunxi_get_sram_id(); |
| 29 | |
| 30 | if (IS_ENABLED(CONFIG_MACH_SUN8I_A23)) { |
| 31 | if (version == 0x1650) |
| 32 | setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); |
| 33 | else /* 0x1661 ? */ |
| 34 | setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); |
| 35 | } else if (IS_ENABLED(CONFIG_MACH_SUN8I_A33)) { |
| 36 | if (version != 0x1667) |
| 37 | setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); |
| 38 | } |
| 39 | } |
| 40 | } |