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git01.mediatek.com / filogic / uboot / d4b57ec1d154916492fefd33ded0b3c2a7daff00 / . / arch / arm / cpu / armv7 / ls102xa / fsl_epu.c
blob: 664eae532d5f9e933abbe900924abb62cbae4cf9 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
chenhui zhao0c789872014-10-22 18:20:22 +0800[diff] [blame]2/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
chenhui zhao0c789872014-10-22 18:20:22 +0800[diff] [blame]4 */
5
chenhui zhao0c789872014-10-22 18:20:22 +0800[diff] [blame]6#include <asm/io.h>
7
8#include "fsl_epu.h"
9
Hongbo Zhang4ea6d6f2016-08-19 17:20:32 +0800[diff] [blame]10struct fsm_reg_vals epu_default_val[] = {
11 /* EPGCR (Event Processor Global Control Register) */
12 {EPGCR, 0},
13 /* EPECR (Event Processor Event Control Registers) */
14 {EPECR0 + EPECR_STRIDE * 0, 0},
15 {EPECR0 + EPECR_STRIDE * 1, 0},
16 {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
17 {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
18 {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
19 {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
20 {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
21 {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
22 {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
23 {EPECR0 + EPECR_STRIDE * 9, 0x08000084},
24 {EPECR0 + EPECR_STRIDE * 10, 0x42000084},
25 {EPECR0 + EPECR_STRIDE * 11, 0x90000084},
26 {EPECR0 + EPECR_STRIDE * 12, 0x80000084},
27 {EPECR0 + EPECR_STRIDE * 13, 0x08000084},
28 {EPECR0 + EPECR_STRIDE * 14, 0x02000084},
29 {EPECR0 + EPECR_STRIDE * 15, 0x00000004},
30 /*
31 * EPEVTCR (Event Processor EVT Pin Control Registers)
32 * SCU8 triger EVT2, and SCU11 triger EVT9
33 */
34 {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
35 {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
36 {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
37 {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
38 {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
39 {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
40 {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
41 {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
42 {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
43 {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
44 /* EPCMPR (Event Processor Counter Compare Registers) */
45 {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
46 {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
47 {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
48 {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
49 {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
50 {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
51 {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
52 {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
53 {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
54 {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
55 {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
56 {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
57 {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
58 {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
59 {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
60 {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
61 /* EPCCR (Event Processor Counter Control Registers) */
62 {EPCCR0 + EPCCR_STRIDE * 0, 0},
63 {EPCCR0 + EPCCR_STRIDE * 1, 0},
64 {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
65 {EPCCR0 + EPCCR_STRIDE * 3, 0},
66 {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
67 {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
68 {EPCCR0 + EPCCR_STRIDE * 6, 0},
69 {EPCCR0 + EPCCR_STRIDE * 7, 0},
70 {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
71 {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
72 {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
73 {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
74 {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
75 {EPCCR0 + EPCCR_STRIDE * 13, 0},
76 {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
77 {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
78 /* EPSMCR (Event Processor SCU Mux Control Registers) */
79 {EPSMCR0 + EPSMCR_STRIDE * 0, 0},
80 {EPSMCR0 + EPSMCR_STRIDE * 1, 0},
81 {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
82 {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
83 {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
84 {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
85 {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
86 {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
87 {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
88 {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
89 {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
90 {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
91 {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
92 {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
93 {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
94 {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
95 /* EPACR (Event Processor Action Control Registers) */
96 {EPACR0 + EPACR_STRIDE * 0, 0},
97 {EPACR0 + EPACR_STRIDE * 1, 0},
98 {EPACR0 + EPACR_STRIDE * 2, 0},
99 {EPACR0 + EPACR_STRIDE * 3, 0x00000080},
100 {EPACR0 + EPACR_STRIDE * 4, 0},
101 {EPACR0 + EPACR_STRIDE * 5, 0x00000040},
102 {EPACR0 + EPACR_STRIDE * 6, 0},
103 {EPACR0 + EPACR_STRIDE * 7, 0},
104 {EPACR0 + EPACR_STRIDE * 8, 0},
105 {EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
106 {EPACR0 + EPACR_STRIDE * 10, 0x00000020},
107 {EPACR0 + EPACR_STRIDE * 11, 0},
108 {EPACR0 + EPACR_STRIDE * 12, 0x00000003},
109 {EPACR0 + EPACR_STRIDE * 13, 0x06000000},
110 {EPACR0 + EPACR_STRIDE * 14, 0x04000000},
111 {EPACR0 + EPACR_STRIDE * 15, 0x02000000},
112 /* EPIMCR (Event Processor Input Mux Control Registers) */
113 {EPIMCR0 + EPIMCR_STRIDE * 0, 0},
114 {EPIMCR0 + EPIMCR_STRIDE * 1, 0},
115 {EPIMCR0 + EPIMCR_STRIDE * 2, 0},
116 {EPIMCR0 + EPIMCR_STRIDE * 3, 0},
117 {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
118 {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
119 {EPIMCR0 + EPIMCR_STRIDE * 6, 0},
120 {EPIMCR0 + EPIMCR_STRIDE * 7, 0},
121 {EPIMCR0 + EPIMCR_STRIDE * 8, 0},
122 {EPIMCR0 + EPIMCR_STRIDE * 9, 0},
123 {EPIMCR0 + EPIMCR_STRIDE * 10, 0},
124 {EPIMCR0 + EPIMCR_STRIDE * 11, 0},
125 {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
126 {EPIMCR0 + EPIMCR_STRIDE * 13, 0},
127 {EPIMCR0 + EPIMCR_STRIDE * 14, 0},
128 {EPIMCR0 + EPIMCR_STRIDE * 15, 0},
129 {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
130 {EPIMCR0 + EPIMCR_STRIDE * 17, 0},
131 {EPIMCR0 + EPIMCR_STRIDE * 18, 0},
132 {EPIMCR0 + EPIMCR_STRIDE * 19, 0},
133 {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
134 {EPIMCR0 + EPIMCR_STRIDE * 21, 0},
135 {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
136 {EPIMCR0 + EPIMCR_STRIDE * 23, 0},
137 {EPIMCR0 + EPIMCR_STRIDE * 24, 0},
138 {EPIMCR0 + EPIMCR_STRIDE * 25, 0},
139 {EPIMCR0 + EPIMCR_STRIDE * 26, 0},
140 {EPIMCR0 + EPIMCR_STRIDE * 27, 0},
141 {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
142 {EPIMCR0 + EPIMCR_STRIDE * 29, 0},
143 {EPIMCR0 + EPIMCR_STRIDE * 30, 0},
144 {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
145 /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
146 {EPXTRIGCR, 0x0000FFDF},
147 /* end */
148 {FSM_END_FLAG, 0},
149};
150
151/**
152 * fsl_epu_setup - Setup EPU registers to default values
153 */
154void fsl_epu_setup(void *epu_base)
155{
156 struct fsm_reg_vals *data = epu_default_val;
157
158 if (!epu_base || !data)
159 return;
160
161 while (data->offset != FSM_END_FLAG) {
162 out_be32(epu_base + data->offset, data->value);
163 data++;
164 }
165}
166
chenhui zhao0c789872014-10-22 18:20:22 +0800[diff] [blame]167/**
168 * fsl_epu_clean - Clear EPU registers
169 */
170void fsl_epu_clean(void *epu_base)
171{
172 u32 offset;
173
174 /* follow the exact sequence to clear the registers */
175 /* Clear EPACRn */
176 for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
177 out_be32(epu_base + offset, 0);
178
179 /* Clear EPEVTCRn */
180 for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
181 out_be32(epu_base + offset, 0);
182
183 /* Clear EPGCR */
184 out_be32(epu_base + EPGCR, 0);
185
186 /* Clear EPSMCRn */
187 for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
188 out_be32(epu_base + offset, 0);
189
190 /* Clear EPCCRn */
191 for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
192 out_be32(epu_base + offset, 0);
193
194 /* Clear EPCMPRn */
195 for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
196 out_be32(epu_base + offset, 0);
197
198 /* Clear EPCTRn */
199 for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
200 out_be32(epu_base + offset, 0);
201
202 /* Clear EPIMCRn */
203 for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
204 out_be32(epu_base + offset, 0);
205
206 /* Clear EPXTRIGCRn */
207 out_be32(epu_base + EPXTRIGCR, 0);
208
209 /* Clear EPECRn */
210 for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
211 out_be32(epu_base + offset, 0);
212}