blob: 505aa0646bc9976cdb76625ceedcabc4084e4b22 [file] [log] [blame]
Jiaxun Yangb2c05382024-06-18 14:56:09 +01001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2007-2013 Tensilica, Inc.
4 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
5 * Copyright (C) 2024 Jiaxun Yang <jiaxun.yang@flygoat.com>
6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#include <asm/arch/core.h>
12#include <asm/addrspace.h>
13#include <asm/config.h>
14
15#if XCHAL_HAVE_PTP_MMU
16#define CFG_SYS_MEMORY_BASE \
17 (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
18#define CFG_SYS_IO_BASE 0xf0000000
19#define CFG_SYS_SDRAM_SIZE 0x80000000 /* xtensa.sysram0 */
20#else
21#define CFG_SYS_MEMORY_BASE 0x60000000
22#define CFG_SYS_SDRAM_SIZE 0x08000000 /* xtensa.sysram0 */
23#endif
24
25#define CFG_SYS_SDRAM_BASE MEMADDR(0x00000000)
26
27#if defined(CFG_MAX_MEM_MAPPED) && \
28 CFG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE
29#define XTENSA_SYS_TEXT_ADDR \
30 (MEMADDR(CFG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN)
31#else
32#define XTENSA_SYS_TEXT_ADDR \
33 (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN)
34#endif
35
36#endif /* __CONFIG_H */