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Michal Simekf0e47692021-07-30 08:00:10 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Xilinx, Inc. - Michal Simek
4 */
5
6#define LOG_CATEGORY UCLASS_RESET
7
Michal Simekf0e47692021-07-30 08:00:10 +02008#include <dm.h>
9#include <dm/device_compat.h>
10#include <reset-uclass.h>
11#include <zynqmp_firmware.h>
12
13#define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
14#define ZYNQMP_RESET_ID ZYNQMP_PM_RESET_START
15
16struct zynqmp_reset_priv {
17 u32 reset_id;
18 u32 nr_reset;
19};
20
21static int zynqmp_pm_reset_assert(const u32 reset,
22 const enum zynqmp_pm_reset_action assert_flag)
23{
24 return xilinx_pm_request(PM_RESET_ASSERT, reset, assert_flag, 0, 0,
25 NULL);
26}
27
28static int zynqmp_reset_assert(struct reset_ctl *rst)
29{
30 struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev);
31
32 dev_dbg(rst->dev, "%s(rst=%p) (id=%lu)\n", __func__, rst, rst->id);
33
34 return zynqmp_pm_reset_assert(priv->reset_id + rst->id,
35 PM_RESET_ACTION_ASSERT);
36}
37
38static int zynqmp_reset_deassert(struct reset_ctl *rst)
39{
40 struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev);
41
42 dev_dbg(rst->dev, "%s(rst=%p) (id=%lu)\n", __func__, rst, rst->id);
43
44 return zynqmp_pm_reset_assert(priv->reset_id + rst->id,
45 PM_RESET_ACTION_RELEASE);
46}
47
48static int zynqmp_reset_request(struct reset_ctl *rst)
49{
50 struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev);
51
52 dev_dbg(rst->dev, "%s(rst=%p) (id=%lu) (nr_reset=%d)\n", __func__,
53 rst, rst->id, priv->nr_reset);
54
T Karthik Reddya3a4cc82022-07-20 03:59:57 -060055 if (priv->nr_reset && rst->id > priv->nr_reset)
Michal Simekf0e47692021-07-30 08:00:10 +020056 return -EINVAL;
57
58 return 0;
59}
60
Michal Simekf0e47692021-07-30 08:00:10 +020061static int zynqmp_reset_probe(struct udevice *dev)
62{
63 struct zynqmp_reset_priv *priv = dev_get_priv(dev);
64
T Karthik Reddya3a4cc82022-07-20 03:59:57 -060065 if (device_is_compatible(dev, "xlnx,zynqmp-reset")) {
66 priv->reset_id = ZYNQMP_RESET_ID;
67 priv->nr_reset = ZYNQMP_NR_RESETS;
68 }
69
Michal Simekf0e47692021-07-30 08:00:10 +020070 return 0;
71}
72
73const struct reset_ops zynqmp_reset_ops = {
74 .request = zynqmp_reset_request,
Michal Simekf0e47692021-07-30 08:00:10 +020075 .rst_assert = zynqmp_reset_assert,
76 .rst_deassert = zynqmp_reset_deassert,
77};
78
79static const struct udevice_id zynqmp_reset_ids[] = {
80 { .compatible = "xlnx,zynqmp-reset" },
T Karthik Reddya3a4cc82022-07-20 03:59:57 -060081 { .compatible = "xlnx,versal-reset" },
Jay Buddhabhattidac2b172022-09-19 14:21:08 +020082 { .compatible = "xlnx,versal-net-reset" },
Michal Simekf0e47692021-07-30 08:00:10 +020083 { }
84};
85
86U_BOOT_DRIVER(zynqmp_reset) = {
87 .name = "zynqmp_reset",
88 .id = UCLASS_RESET,
89 .of_match = zynqmp_reset_ids,
90 .ops = &zynqmp_reset_ops,
91 .probe = zynqmp_reset_probe,
92 .priv_auto = sizeof(struct zynqmp_reset_priv),
93};