blob: 496f4628d34ff01827291078d25533eb57b13521 [file] [log] [blame]
Andy Yanb5e16302019-11-14 11:21:12 +08001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6#ifndef __CONFIG_RK3308_COMMON_H
7#define __CONFIG_RK3308_COMMON_H
8
9#include "rockchip-common.h"
10
11#define CONFIG_SYS_CBSIZE 1024
Andy Yanb5e16302019-11-14 11:21:12 +080012#define CONFIG_SPL_MAX_SIZE 0x20000
13#define CONFIG_SPL_BSS_START_ADDR 0x00400000
14#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
15#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
16
17#define CONFIG_SYS_NS16550_MEM32
18
19#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0
20#define CONFIG_IRAM_BASE 0xfff80000
21#define CONFIG_SYS_INIT_SP_ADDR 0x00800000
Andy Yanb5e16302019-11-14 11:21:12 +080022#define CONFIG_SPL_STACK 0x00400000
23#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
24
25#define COUNTER_FREQUENCY 24000000
26
27#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
28
29#define CONFIG_SYS_SDRAM_BASE 0
30#define SDRAM_MAX_SIZE 0xff000000
31#define SDRAM_BANK_SIZE (2UL << 30)
32
33#ifndef CONFIG_SPL_BUILD
34
35#define ENV_MEM_LAYOUT_SETTINGS \
36 "scriptaddr=0x00500000\0" \
37 "pxefile_addr_r=0x00600000\0" \
Andy Yan038626e2019-12-26 15:20:04 +080038 "fdt_addr_r=0x02800000\0" \
Andy Yanb5e16302019-11-14 11:21:12 +080039 "kernel_addr_r=0x00680000\0" \
40 "ramdisk_addr_r=0x04000000\0"
41
42#include <config_distro_bootcmd.h>
43#define CONFIG_EXTRA_ENV_SETTINGS \
44 ENV_MEM_LAYOUT_SETTINGS \
45 "partitions=" PARTS_DEFAULT \
46 ROCKCHIP_DEVICE_SETTINGS \
47 BOOTENV
48
49#endif
50
51#endif