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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
TsiChung Liewe7e4fc82008-10-22 11:38:21 +00002/*
3 * Configuation settings for the Freescale MCF53017EVB.
4 *
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liewe7e4fc82008-10-22 11:38:21 +00007 */
8
9/*
10 * board/config.h - configuration options, board specific
11 */
12
13#ifndef _M53017EVB_H
14#define _M53017EVB_H
15
16/*
17 * High Level Configuration Options
18 * (easy to change)
19 */
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000020
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000021#define CONFIG_SYS_UART_PORT (0)
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000022
23#undef CONFIG_WATCHDOG
24#define CONFIG_WATCHDOG_TIMEOUT 5000
25
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000026#define CONFIG_SYS_UNIFY_CACHE
27
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000028#ifdef CONFIG_MCFFEC
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000029# define CONFIG_MII_INIT 1
30# define CONFIG_SYS_DISCOVER_PHY
31# define CONFIG_SYS_RX_ETH_BUFFER 8
TsiChung Liew4ebe03c2010-03-10 18:24:07 -060032# define CONFIG_SYS_TX_ETH_BUFFER 8
33# define CONFIG_SYS_FEC_BUF_USE_SRAM
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000034# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
35# define CONFIG_HAS_ETH1
36
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000037/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
38# ifndef CONFIG_SYS_DISCOVER_PHY
39# define FECDUPLEX FULL
40# define FECSPEED _100BASET
41# else
42# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
43# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
44# endif
45# endif /* CONFIG_SYS_DISCOVER_PHY */
46#endif
47
48#define CONFIG_MCFRTC
49#undef RTC_DEBUG
50#define CONFIG_SYS_RTC_CNT (0x8000)
51#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
52
53/* Timer */
54#define CONFIG_MCFTMR
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000055
56/* I2C */
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000057#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
58
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000059#define CONFIG_UDP_CHECKSUM
60
61#ifdef CONFIG_MCFFEC
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000062# define CONFIG_IPADDR 192.162.1.2
63# define CONFIG_NETMASK 255.255.255.0
64# define CONFIG_SERVERIP 192.162.1.1
65# define CONFIG_GATEWAYIP 192.162.1.1
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000066#endif /* FEC_ENET */
67
Mario Six790d8442018-03-28 14:38:20 +020068#define CONFIG_HOSTNAME "M53017"
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000069#define CONFIG_EXTRA_ENV_SETTINGS \
70 "netdev=eth0\0" \
71 "loadaddr=40010000\0" \
72 "u-boot=u-boot.bin\0" \
73 "load=tftp ${loadaddr) ${u-boot}\0" \
74 "upd=run load; run prog\0" \
75 "prog=prot off 0 3ffff;" \
76 "era 0 3ffff;" \
77 "cp.b ${loadaddr} 0 ${filesize};" \
78 "save\0" \
79 ""
80
81#define CONFIG_PRAM 512 /* 512 KB */
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000082
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000083#define CONFIG_SYS_CLK 80000000
84#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
85
86#define CONFIG_SYS_MBAR 0xFC000000
87
88/*
89 * Low Level Configuration Settings
90 * (address mappings, register initial values, etc.)
91 * You should know what you are doing if you make changes here.
92 */
93/*
94 * Definitions for initial stack pointer and data area (in DPRAM)
95 */
96#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +020097#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
TsiChung Liew4ebe03c2010-03-10 18:24:07 -060098#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Denk0191e472010-10-26 14:34:52 +020099#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000100#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
101
102/*
103 * Start addresses for the final memory configuration
104 * (Set up by the startup code)
105 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
106 */
107#define CONFIG_SYS_SDRAM_BASE 0x40000000
108#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
109#define CONFIG_SYS_SDRAM_CFG1 0x43711630
110#define CONFIG_SYS_SDRAM_CFG2 0x56670000
TsiChung Liew4ebe03c2010-03-10 18:24:07 -0600111#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000112#define CONFIG_SYS_SDRAM_EMOD 0x80010000
113#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
114
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000115#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
116#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
117
118#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000119
120/*
121 * For booting Linux, the board info and command line data
122 * have to be in the first 8 MB of memory, since this is
123 * the maximum mapped by the Linux kernel during initialization ??
124 */
125#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liew25a00632009-01-27 12:57:47 +0000126#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000127
128/*-----------------------------------------------------------------------
129 * FLASH organization
130 */
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000131#ifdef CONFIG_SYS_FLASH_CFI
TsiChung Liewb7d482b2009-06-11 12:50:05 +0000132# define CONFIG_FLASH_SPANSION_S29WS_N 1
TsiChung Liewcec0c4a2009-06-12 11:31:31 +0000133# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000134# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
135# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
136# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000137#endif
138
139#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
140
141/* Configuration for environment
142 * Environment is embedded in u-boot in the second sector of the flash
143 */
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000144
angelo@sysam.it6312a952015-03-29 22:54:16 +0200145#define LDS_BOARD_TEXT \
146 . = DEFINED(env_offset) ? env_offset : .; \
Simon Glass547cb402017-08-03 12:21:49 -0600147 env/embedded.o(.text*)
angelo@sysam.it6312a952015-03-29 22:54:16 +0200148
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000149/*-----------------------------------------------------------------------
150 * Cache Configuration
151 */
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000152
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600153#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200154 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600155#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200156 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600157#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
158#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
159 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
160 CF_ACR_EN | CF_ACR_SM_ALL)
161#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
162 CF_CACR_DCM_P)
163
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000164/*-----------------------------------------------------------------------
165 * Chipselect bank definitions
166 */
167/*
168 * CS0 - NOR Flash
169 * CS1 - Ext SRAM
170 * CS2 - Available
171 * CS3 - Available
172 * CS4 - Available
173 * CS5 - Available
174 */
175#define CONFIG_SYS_CS0_BASE 0
176#define CONFIG_SYS_CS0_MASK 0x00FF0001
177#define CONFIG_SYS_CS0_CTRL 0x00001FA0
178
179#define CONFIG_SYS_CS1_BASE 0xC0000000
180#define CONFIG_SYS_CS1_MASK 0x00070001
181#define CONFIG_SYS_CS1_CTRL 0x00001FA0
182
183#endif /* _M53017EVB_H */