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git01.mediatek.com / filogic / uboot / d492090919743009511734735f6c91bfb8632430 / . / board / cloudengines / pogo_v4 / pogo_v4.c
blob: c8ad563f721deca364553e81db386ffea61a38f1 [file] [log] [blame]
Tony Dinh6e36f662022-01-23 22:17:12 -0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2014-2022 Tony Dinh <mibodhi@gmail.com>
4 *
5 * Based on
6 * Copyright (C) 2012 David Purdy <david.c.purdy@gmail.com>
7 *
8 * Based on Kirkwood support:
9 * (C) Copyright 2009
10 * Marvell Semiconductor <www.marvell.com>
11 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
12 */
13
Tony Dinh6e36f662022-01-23 22:17:12 -0800[diff] [blame]14#include <netdev.h>
15#include <asm/arch/cpu.h>
16#include <asm/arch/soc.h>
17#include <asm/arch/mpp.h>
18#include <asm/io.h>
19#include <asm/arch/gpio.h>
20#include <asm/mach-types.h>
21#include <bootstage.h>
22#include <command.h>
23#include <init.h>
24#include <linux/bitops.h>
25
26DECLARE_GLOBAL_DATA_PTR;
27
28/* GPIO configuration */
29#define POGO_V4_OE_LOW (~(0))
30#define POGO_V4_OE_HIGH (~(0))
31#define POGO_V4_OE_VAL_LOW BIT(29)
32#define POGO_V4_OE_VAL_HIGH 0
33
34/* button */
35#define BTN_EJECT 29
36
37int board_early_init_f(void)
38{
39 /*
40 * default gpio configuration
41 * There are maximum 64 gpios controlled through 2 sets of registers
42 * the below configuration configures mainly initial LED status
43 */
44 mvebu_config_gpio(POGO_V4_OE_VAL_LOW,
45 POGO_V4_OE_VAL_HIGH,
46 POGO_V4_OE_LOW, POGO_V4_OE_HIGH);
47
48 /* Multi-Purpose Pins Functionality configuration */
49 u32 kwmpp_config[] = {
50 MPP0_NF_IO2,
51 MPP1_NF_IO3,
52 MPP2_NF_IO4,
53 MPP3_NF_IO5,
54 MPP4_NF_IO6,
55 MPP5_NF_IO7,
56 MPP6_SYSRST_OUTn,
57 MPP7_GPO,
58 MPP8_TW_SDA,
59 MPP9_TW_SCK,
60 MPP10_UART0_TXD,
61 MPP11_UART0_RXD,
62 MPP12_SD_CLK,
63 MPP13_SD_CMD,
64 MPP14_SD_D0,
65 MPP15_SD_D1,
66 MPP16_SD_D2,
67 MPP17_SD_D3,
68 MPP18_NF_IO0,
69 MPP19_NF_IO1,
70 MPP20_SATA1_ACTn,
71 MPP21_SATA0_ACTn,
72 MPP22_GPIO, /* Green LED */
73 MPP23_GPIO,
74 MPP24_GPIO, /* Red LED */
75 MPP25_GPIO,
76 MPP26_GPIO,
77 MPP27_GPIO,
78 MPP28_GPIO,
79 MPP29_GPIO, /* Eject button */
80 MPP30_GPIO,
81 MPP31_GPIO,
82 MPP32_GPIO,
83 MPP33_GPIO,
84 MPP34_GPIO,
85 MPP35_GPIO, /* FR6192 has only 36 GPIOs */
86 0
87 };
88 kirkwood_mpp_conf(kwmpp_config, NULL);
89
90 return 0;
91}
92
93int board_eth_init(struct bd_info *bis)
94{
95 return cpu_eth_init(bis);
96}
97
98int board_late_init(void)
99{
100 /* Do late init to ensure successful enumeration of XHCI devices */
101 pci_init();
102 return 0;
103}
104
105int board_init(void)
106{
107 /* Boot parameters address */
108 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
109
110 return 0;
111}
112
113#if CONFIG_IS_ENABLED(BOOTSTAGE)
114#define GREEN_LED BIT(22)
115#define RED_LED BIT(24)
116#define BOTH_LEDS (GREEN_LED | RED_LED)
117#define NEITHER_LED 0
118
119static void set_leds(u32 leds, u32 blinking)
120{
121 struct kwgpio_registers *r;
122 u32 oe;
123 u32 bl;
124
125 r = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
126 oe = readl(&r->oe) | BOTH_LEDS;
127 writel(oe & ~leds, &r->oe); /* active low */
128 bl = readl(&r->blink_en) & ~BOTH_LEDS;
129 writel(bl | blinking, &r->blink_en);
130}
131
132void show_boot_progress(int val)
133{
134 switch (val) {
135 case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
136 set_leds(BOTH_LEDS, NEITHER_LED);
137 break;
138 case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
139 set_leds(GREEN_LED, GREEN_LED);
140 break;
141 default:
142 if (val < 0) /* error */
143 set_leds(RED_LED, RED_LED);
144 break;
145 }
146}
147#endif