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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mateusz Kulikowski2507d822016-03-31 23:12:32 +02002/*
3 * Qualcomm APQ8916 sysmap
4 *
5 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Mateusz Kulikowski2507d822016-03-31 23:12:32 +02006 */
7#ifndef _MACH_SYSMAP_APQ8016_H
8#define _MACH_SYSMAP_APQ8016_H
9
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +010010#define GICD_BASE (0x0b000000)
Sheep Sun5eec8872021-06-20 10:34:34 +080011#define GICC_BASE (0x0b002000)
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +010012
13/* Clocks: (from CLK_CTL_BASE) */
14#define GPLL0_STATUS (0x2101C)
15#define APCS_GPLL_ENA_VOTE (0x45000)
Ramon Friedae299772018-05-16 12:13:39 +030016#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +010017
18#define SDCC_BCR(n) ((n * 0x1000) + 0x41000)
19#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004)
20#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008)
21#define SDCC_M(n) ((n * 0x1000) + 0x4100C)
22#define SDCC_N(n) ((n * 0x1000) + 0x41010)
23#define SDCC_D(n) ((n * 0x1000) + 0x41014)
24#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018)
25#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C)
26
27/* BLSP1 AHB clock (root clock for BLSP) */
28#define BLSP1_AHB_CBCR 0x1008
29
30/* Uart clock control registers */
31#define BLSP1_UART2_BCR (0x3028)
32#define BLSP1_UART2_APPS_CBCR (0x302C)
33#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
34#define BLSP1_UART2_APPS_CFG_RCGR (0x3038)
35#define BLSP1_UART2_APPS_M (0x303C)
36#define BLSP1_UART2_APPS_N (0x3040)
37#define BLSP1_UART2_APPS_D (0x3044)
Mateusz Kulikowski2507d822016-03-31 23:12:32 +020038
39#endif