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git01.mediatek.com / filogic / uboot / d48f49b207b2225d3c90c0a6735ae4239f46af80 / . / arch / arm / dts / nuvoton-common-npcm7xx.dtsi
blob: feb88872fc712efb9e30f99c957c808f5edb003d [file] [log] [blame]
Jim Liu4359b332022-04-19 13:32:19 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2
3#include <dt-bindings/interrupt-controller/arm-gic.h>
4#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
5#include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
6
7/ {
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
11
12 /* external reference clock */
13 clk_refclk: clk_refclk {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <25000000>;
17 clock-output-names = "refclk";
18 };
19
20 /* external reference clock for cpu. float in normal operation */
21 clk_sysbypck: clk_sysbypck {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <800000000>;
25 clock-output-names = "sysbypck";
26 };
27
28 /* external reference clock for MC. float in normal operation */
29 clk_mcbypck: clk_mcbypck {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <800000000>;
33 clock-output-names = "mcbypck";
34 };
35
36 /* external clock signal rg1refck, supplied by the phy */
37 clk_rg1refck: clk_rg1refck {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <125000000>;
41 clock-output-names = "clk_rg1refck";
42 };
43
44 /* external clock signal rg2refck, supplied by the phy */
45 clk_rg2refck: clk_rg2refck {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <125000000>;
49 clock-output-names = "clk_rg2refck";
50 };
51
52 clk_xin: clk_xin {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <50000000>;
56 clock-output-names = "clk_xin";
57 };
58
59 soc {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "simple-bus";
63 interrupt-parent = <&gic>;
64 ranges = <0x0 0xf0000000 0x00900000>;
65
66 scu: scu@3fe000 {
67 compatible = "arm,cortex-a9-scu";
68 reg = <0x3fe000 0x1000>;
69 };
70
71 l2: cache-controller@3fc000 {
72 compatible = "arm,pl310-cache";
73 reg = <0x3fc000 0x1000>;
74 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
75 cache-unified;
76 cache-level = <2>;
77 clocks = <&clk NPCM7XX_CLK_AXI>;
78 arm,shared-override;
79 };
80
81 gic: interrupt-controller@3ff000 {
82 compatible = "arm,cortex-a9-gic";
83 interrupt-controller;
84 #interrupt-cells = <3>;
85 reg = <0x3ff000 0x1000>,
86 <0x3fe100 0x100>;
87 };
88
89 gcr: gcr@800000 {
90 compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd";
91 reg = <0x800000 0x1000>;
92 };
93
94 rst: rst@801000 {
95 compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd";
96 reg = <0x801000 0x6C>;
97 };
98 };
99
100 ahb {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 compatible = "simple-bus";
104 interrupt-parent = <&gic>;
105 ranges;
106
107 rstc: rstc@f0801000 {
108 compatible = "nuvoton,npcm750-reset";
109 reg = <0xf0801000 0x70>;
110 #reset-cells = <2>;
111 };
112
113 clk: clock-controller@f0801000 {
114 compatible = "nuvoton,npcm750-clk", "syscon";
115 #clock-cells = <1>;
116 clock-controller;
117 reg = <0xf0801000 0x1000>;
118 clock-names = "refclk", "sysbypck", "mcbypck";
119 clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
120 };
121
122 gmac0: eth@f0802000 {
123 device_type = "network";
124 compatible = "nuvoton,npcm-dwmac";
125 reg = <0xf0802000 0x2000>;
126 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
127 interrupt-names = "macirq";
128 ethernet = <0>;
129 clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
130 clock-names = "stmmaceth", "clk_gmac";
131 pinctrl-names = "default";
132 pinctrl-0 = <&rg1_pins
133 &rg1mdio_pins>;
134 status = "disabled";
135 };
136
137 ehci1: usb@f0806000 {
138 compatible = "nuvoton,npcm750-ehci";
139 reg = <0xf0806000 0x1000>;
140 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
141 status = "disabled";
142 };
143
144 fiu0: spi@fb000000 {
145 compatible = "nuvoton,npcm750-fiu";
146 #address-cells = <1>;
147 #size-cells = <0>;
148 reg = <0xfb000000 0x1000>;
149 reg-names = "control", "memory";
150 clocks = <&clk NPCM7XX_CLK_SPI0>;
151 clock-names = "clk_spi0";
152 status = "disabled";
153 };
154
155 fiu3: spi@c0000000 {
156 compatible = "nuvoton,npcm750-fiu";
157 #address-cells = <1>;
158 #size-cells = <0>;
159 reg = <0xc0000000 0x1000>;
160 reg-names = "control", "memory";
161 clocks = <&clk NPCM7XX_CLK_SPI3>;
162 clock-names = "clk_spi3";
163 pinctrl-names = "default";
164 pinctrl-0 = <&spi3_pins>;
165 status = "disabled";
166 };
167
168 fiux: spi@fb001000 {
169 compatible = "nuvoton,npcm750-fiu";
170 #address-cells = <1>;
171 #size-cells = <0>;
172 reg = <0xfb001000 0x1000>;
173 reg-names = "control", "memory";
174 clocks = <&clk NPCM7XX_CLK_SPIX>;
175 clock-names = "clk_spix";
176 status = "disabled";
177 };
178
179 apb {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 compatible = "simple-bus";
183 interrupt-parent = <&gic>;
184 ranges = <0x0 0xf0000000 0x00300000>;
185
186 lpc_kcs: lpc_kcs@7000 {
187 compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
188 reg = <0x7000 0x40>;
189 reg-io-width = <1>;
190
191 #address-cells = <1>;
192 #size-cells = <1>;
193 ranges = <0x0 0x7000 0x40>;
194
195 kcs1: kcs1@0 {
196 compatible = "nuvoton,npcm750-kcs-bmc";
197 reg = <0x0 0x40>;
198 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
199 kcs_chan = <1>;
200 status = "disabled";
201 };
202
203 kcs2: kcs2@0 {
204 compatible = "nuvoton,npcm750-kcs-bmc";
205 reg = <0x0 0x40>;
206 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
207 kcs_chan = <2>;
208 status = "disabled";
209 };
210
211 kcs3: kcs3@0 {
212 compatible = "nuvoton,npcm750-kcs-bmc";
213 reg = <0x0 0x40>;
214 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
215 kcs_chan = <3>;
216 status = "disabled";
217 };
218 };
219
220 spi0: spi@200000 {
221 compatible = "nuvoton,npcm750-pspi";
222 reg = <0x200000 0x1000>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&pspi1_pins>;
225 #address-cells = <1>;
226 #size-cells = <0>;
227 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&clk NPCM7XX_CLK_APB5>;
229 clock-names = "clk_apb5";
230 resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
231 status = "disabled";
232 };
233
234 spi1: spi@201000 {
235 compatible = "nuvoton,npcm750-pspi";
236 reg = <0x201000 0x1000>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&pspi2_pins>;
239 #address-cells = <1>;
240 #size-cells = <0>;
241 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&clk NPCM7XX_CLK_APB5>;
243 clock-names = "clk_apb5";
244 resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI2>;
245 status = "disabled";
246 };
247
248 timer0: timer@8000 {
249 compatible = "nuvoton,npcm750-timer";
250 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
251 reg = <0x8000 0x1C>;
252 clocks = <&clk NPCM7XX_CLK_TIMER>;
253 };
254
255 watchdog0: watchdog@801C {
256 compatible = "nuvoton,npcm750-wdt";
257 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
258 reg = <0x801C 0x4>;
259 status = "disabled";
260 clocks = <&clk NPCM7XX_CLK_TIMER>;
261 };
262
263 watchdog1: watchdog@901C {
264 compatible = "nuvoton,npcm750-wdt";
265 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
266 reg = <0x901C 0x4>;
267 status = "disabled";
268 clocks = <&clk NPCM7XX_CLK_TIMER>;
269 };
270
271 watchdog2: watchdog@a01C {
272 compatible = "nuvoton,npcm750-wdt";
273 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
274 reg = <0xa01C 0x4>;
275 status = "disabled";
276 clocks = <&clk NPCM7XX_CLK_TIMER>;
277 };
278
279 serial0: serial@1000 {
280 compatible = "nuvoton,npcm750-uart";
281 reg = <0x1000 0x1000>;
282 clocks = <&clk NPCM7XX_CLK_UART>, <&clk NPCM7XX_CLK_PLL2DIV2>;
283 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
284 reg-shift = <2>;
285 status = "disabled";
286 };
287
288 serial1: serial@2000 {
289 compatible = "nuvoton,npcm750-uart";
290 reg = <0x2000 0x1000>;
291 clocks = <&clk NPCM7XX_CLK_UART>, <&clk NPCM7XX_CLK_PLL2DIV2>;
292 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
293 reg-shift = <2>;
294 status = "disabled";
295 };
296
297 serial2: serial@3000 {
298 compatible = "nuvoton,npcm750-uart";
299 reg = <0x3000 0x1000>;
300 clocks = <&clk NPCM7XX_CLK_UART>, <&clk NPCM7XX_CLK_PLL2DIV2>;
301 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
302 reg-shift = <2>;
303 status = "disabled";
304 };
305
306 serial3: serial@4000 {
307 compatible = "nuvoton,npcm750-uart";
308 reg = <0x4000 0x1000>;
309 clocks = <&clk NPCM7XX_CLK_UART>, <&clk NPCM7XX_CLK_PLL2DIV2>;
310 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
311 reg-shift = <2>;
312 status = "disabled";
313 };
314
315 rng: rng@b000 {
316 compatible = "nuvoton,npcm750-rng";
317 reg = <0xb000 0x8>;
318 status = "disabled";
319 };
320
321 adc: adc@c000 {
322 compatible = "nuvoton,npcm750-adc";
323 reg = <0xc000 0x8>;
324 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&clk NPCM7XX_CLK_ADC>;
326 resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>;
327 status = "disabled";
328 };
329
330 pwm_fan: pwm-fan-controller@103000 {
331 #address-cells = <1>;
332 #size-cells = <0>;
333 compatible = "nuvoton,npcm750-pwm-fan";
334 reg = <0x103000 0x2000>, <0x180000 0x8000>;
335 reg-names = "pwm", "fan";
336 clocks = <&clk NPCM7XX_CLK_APB3>,
337 <&clk NPCM7XX_CLK_APB4>;
338 clock-names = "pwm","fan";
339 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&pwm0_pins &pwm1_pins
349 &pwm2_pins &pwm3_pins
350 &pwm4_pins &pwm5_pins
351 &pwm6_pins &pwm7_pins
352 &fanin0_pins &fanin1_pins
353 &fanin2_pins &fanin3_pins
354 &fanin4_pins &fanin5_pins
355 &fanin6_pins &fanin7_pins
356 &fanin8_pins &fanin9_pins
357 &fanin10_pins &fanin11_pins
358 &fanin12_pins &fanin13_pins
359 &fanin14_pins &fanin15_pins>;
360 status = "disabled";
361 };
362
363 i2c0: i2c@80000 {
364 reg = <0x80000 0x1000>;
365 compatible = "nuvoton,npcm750-i2c";
366 #address-cells = <1>;
367 #size-cells = <0>;
368 clocks = <&clk NPCM7XX_CLK_APB2>;
369 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&smb0_pins>;
372 status = "disabled";
373 };
374
375 i2c1: i2c@81000 {
376 reg = <0x81000 0x1000>;
377 compatible = "nuvoton,npcm750-i2c";
378 #address-cells = <1>;
379 #size-cells = <0>;
380 clocks = <&clk NPCM7XX_CLK_APB2>;
381 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&smb1_pins>;
384 status = "disabled";
385 };
386
387 i2c2: i2c@82000 {
388 reg = <0x82000 0x1000>;
389 compatible = "nuvoton,npcm750-i2c";
390 #address-cells = <1>;
391 #size-cells = <0>;
392 clocks = <&clk NPCM7XX_CLK_APB2>;
393 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&smb2_pins>;
396 status = "disabled";
397 };
398
399 i2c3: i2c@83000 {
400 reg = <0x83000 0x1000>;
401 compatible = "nuvoton,npcm750-i2c";
402 #address-cells = <1>;
403 #size-cells = <0>;
404 clocks = <&clk NPCM7XX_CLK_APB2>;
405 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&smb3_pins>;
408 status = "disabled";
409 };
410
411 i2c4: i2c@84000 {
412 reg = <0x84000 0x1000>;
413 compatible = "nuvoton,npcm750-i2c";
414 #address-cells = <1>;
415 #size-cells = <0>;
416 clocks = <&clk NPCM7XX_CLK_APB2>;
417 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&smb4_pins>;
420 status = "disabled";
421 };
422
423 i2c5: i2c@85000 {
424 reg = <0x85000 0x1000>;
425 compatible = "nuvoton,npcm750-i2c";
426 #address-cells = <1>;
427 #size-cells = <0>;
428 clocks = <&clk NPCM7XX_CLK_APB2>;
429 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&smb5_pins>;
432 status = "disabled";
433 };
434
435 i2c6: i2c@86000 {
436 reg = <0x86000 0x1000>;
437 compatible = "nuvoton,npcm750-i2c";
438 #address-cells = <1>;
439 #size-cells = <0>;
440 clocks = <&clk NPCM7XX_CLK_APB2>;
441 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&smb6_pins>;
444 status = "disabled";
445 };
446
447 i2c7: i2c@87000 {
448 reg = <0x87000 0x1000>;
449 compatible = "nuvoton,npcm750-i2c";
450 #address-cells = <1>;
451 #size-cells = <0>;
452 clocks = <&clk NPCM7XX_CLK_APB2>;
453 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&smb7_pins>;
456 status = "disabled";
457 };
458
459 i2c8: i2c@88000 {
460 reg = <0x88000 0x1000>;
461 compatible = "nuvoton,npcm750-i2c";
462 #address-cells = <1>;
463 #size-cells = <0>;
464 clocks = <&clk NPCM7XX_CLK_APB2>;
465 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
466 pinctrl-names = "default";
467 pinctrl-0 = <&smb8_pins>;
468 status = "disabled";
469 };
470
471 i2c9: i2c@89000 {
472 reg = <0x89000 0x1000>;
473 compatible = "nuvoton,npcm750-i2c";
474 #address-cells = <1>;
475 #size-cells = <0>;
476 clocks = <&clk NPCM7XX_CLK_APB2>;
477 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&smb9_pins>;
480 status = "disabled";
481 };
482
483 i2c10: i2c@8a000 {
484 reg = <0x8a000 0x1000>;
485 compatible = "nuvoton,npcm750-i2c";
486 #address-cells = <1>;
487 #size-cells = <0>;
488 clocks = <&clk NPCM7XX_CLK_APB2>;
489 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&smb10_pins>;
492 status = "disabled";
493 };
494
495 i2c11: i2c@8b000 {
496 reg = <0x8b000 0x1000>;
497 compatible = "nuvoton,npcm750-i2c";
498 #address-cells = <1>;
499 #size-cells = <0>;
500 clocks = <&clk NPCM7XX_CLK_APB2>;
501 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&smb11_pins>;
504 status = "disabled";
505 };
506
507 i2c12: i2c@8c000 {
508 reg = <0x8c000 0x1000>;
509 compatible = "nuvoton,npcm750-i2c";
510 #address-cells = <1>;
511 #size-cells = <0>;
512 clocks = <&clk NPCM7XX_CLK_APB2>;
513 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
514 pinctrl-names = "default";
515 pinctrl-0 = <&smb12_pins>;
516 status = "disabled";
517 };
518
519 i2c13: i2c@8d000 {
520 reg = <0x8d000 0x1000>;
521 compatible = "nuvoton,npcm750-i2c";
522 #address-cells = <1>;
523 #size-cells = <0>;
524 clocks = <&clk NPCM7XX_CLK_APB2>;
525 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
526 pinctrl-names = "default";
527 pinctrl-0 = <&smb13_pins>;
528 status = "disabled";
529 };
530
531 i2c14: i2c@8e000 {
532 reg = <0x8e000 0x1000>;
533 compatible = "nuvoton,npcm750-i2c";
534 #address-cells = <1>;
535 #size-cells = <0>;
536 clocks = <&clk NPCM7XX_CLK_APB2>;
537 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&smb14_pins>;
540 status = "disabled";
541 };
542
543 i2c15: i2c@8f000 {
544 reg = <0x8f000 0x1000>;
545 compatible = "nuvoton,npcm750-i2c";
546 #address-cells = <1>;
547 #size-cells = <0>;
548 clocks = <&clk NPCM7XX_CLK_APB2>;
549 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&smb15_pins>;
552 status = "disabled";
553 };
554 };
555 };
556
557 pinctrl: pinctrl@f0800000 {
558 #address-cells = <1>;
559 #size-cells = <1>;
560 compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd";
561 ranges = <0 0xf0010000 0x8000>;
Jim Liuc7885742022-07-12 17:24:07 +0800[diff] [blame]562 reg = <0xf0010000 0x8000>;
563 syscon-gcr = <&gcr>;
564 syscon-rst = <&rst>;
Jim Liu4359b332022-04-19 13:32:19 +0800[diff] [blame]565 gpio0: gpio@f0010000 {
566 gpio-controller;
567 #gpio-cells = <2>;
568 reg = <0x0 0x80>;
569 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
570 gpio-ranges = <&pinctrl 0 0 32>;
571 };
572 gpio1: gpio@f0011000 {
573 gpio-controller;
574 #gpio-cells = <2>;
575 reg = <0x1000 0x80>;
576 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
577 gpio-ranges = <&pinctrl 0 32 32>;
578 };
579 gpio2: gpio@f0012000 {
580 gpio-controller;
581 #gpio-cells = <2>;
582 reg = <0x2000 0x80>;
583 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
584 gpio-ranges = <&pinctrl 0 64 32>;
585 };
586 gpio3: gpio@f0013000 {
587 gpio-controller;
588 #gpio-cells = <2>;
589 reg = <0x3000 0x80>;
590 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
591 gpio-ranges = <&pinctrl 0 96 32>;
592 };
593 gpio4: gpio@f0014000 {
594 gpio-controller;
595 #gpio-cells = <2>;
596 reg = <0x4000 0x80>;
597 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
598 gpio-ranges = <&pinctrl 0 128 32>;
599 };
600 gpio5: gpio@f0015000 {
601 gpio-controller;
602 #gpio-cells = <2>;
603 reg = <0x5000 0x80>;
604 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
605 gpio-ranges = <&pinctrl 0 160 32>;
606 };
607 gpio6: gpio@f0016000 {
608 gpio-controller;
609 #gpio-cells = <2>;
610 reg = <0x6000 0x80>;
611 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
612 gpio-ranges = <&pinctrl 0 192 32>;
613 };
614 gpio7: gpio@f0017000 {
615 gpio-controller;
616 #gpio-cells = <2>;
617 reg = <0x7000 0x80>;
618 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
619 gpio-ranges = <&pinctrl 0 224 32>;
620 };
621
622 iox1_pins: iox1-pins {
623 groups = "iox1";
624 function = "iox1";
625 };
626 iox2_pins: iox2-pins {
627 groups = "iox2";
628 function = "iox2";
629 };
630 smb1d_pins: smb1d-pins {
631 groups = "smb1d";
632 function = "smb1d";
633 };
634 smb2d_pins: smb2d-pins {
635 groups = "smb2d";
636 function = "smb2d";
637 };
638 lkgpo1_pins: lkgpo1-pins {
639 groups = "lkgpo1";
640 function = "lkgpo1";
641 };
642 lkgpo2_pins: lkgpo2-pins {
643 groups = "lkgpo2";
644 function = "lkgpo2";
645 };
646 ioxh_pins: ioxh-pins {
647 groups = "ioxh";
648 function = "ioxh";
649 };
650 gspi_pins: gspi-pins {
651 groups = "gspi";
652 function = "gspi";
653 };
654 smb5b_pins: smb5b-pins {
655 groups = "smb5b";
656 function = "smb5b";
657 };
658 smb5c_pins: smb5c-pins {
659 groups = "smb5c";
660 function = "smb5c";
661 };
662 lkgpo0_pins: lkgpo0-pins {
663 groups = "lkgpo0";
664 function = "lkgpo0";
665 };
666 pspi2_pins: pspi2-pins {
667 groups = "pspi2";
668 function = "pspi2";
669 };
670 smb4den_pins: smb4den-pins {
671 groups = "smb4den";
672 function = "smb4den";
673 };
674 smb4b_pins: smb4b-pins {
675 groups = "smb4b";
676 function = "smb4b";
677 };
678 smb4c_pins: smb4c-pins {
679 groups = "smb4c";
680 function = "smb4c";
681 };
682 smb15_pins: smb15-pins {
683 groups = "smb15";
684 function = "smb15";
685 };
686 smb4d_pins: smb4d-pins {
687 groups = "smb4d";
688 function = "smb4d";
689 };
690 smb14_pins: smb14-pins {
691 groups = "smb14";
692 function = "smb14";
693 };
694 smb5_pins: smb5-pins {
695 groups = "smb5";
696 function = "smb5";
697 };
698 smb4_pins: smb4-pins {
699 groups = "smb4";
700 function = "smb4";
701 };
702 smb3_pins: smb3-pins {
703 groups = "smb3";
704 function = "smb3";
705 };
706 spi0cs1_pins: spi0cs1-pins {
707 groups = "spi0cs1";
708 function = "spi0cs1";
709 };
710 spi0cs2_pins: spi0cs2-pins {
711 groups = "spi0cs2";
712 function = "spi0cs2";
713 };
714 spi0cs3_pins: spi0cs3-pins {
715 groups = "spi0cs3";
716 function = "spi0cs3";
717 };
718 smb3c_pins: smb3c-pins {
719 groups = "smb3c";
720 function = "smb3c";
721 };
722 smb3b_pins: smb3b-pins {
723 groups = "smb3b";
724 function = "smb3b";
725 };
726 bmcuart0a_pins: bmcuart0a-pins {
727 groups = "bmcuart0a";
728 function = "bmcuart0a";
729 };
730 uart1_pins: uart1-pins {
731 groups = "uart1";
732 function = "uart1";
733 };
734 jtag2_pins: jtag2-pins {
735 groups = "jtag2";
736 function = "jtag2";
737 };
738 bmcuart1_pins: bmcuart1-pins {
739 groups = "bmcuart1";
740 function = "bmcuart1";
741 };
742 uart2_pins: uart2-pins {
743 groups = "uart2";
744 function = "uart2";
745 };
746 bmcuart0b_pins: bmcuart0b-pins {
747 groups = "bmcuart0b";
748 function = "bmcuart0b";
749 };
750 r1err_pins: r1err-pins {
751 groups = "r1err";
752 function = "r1err";
753 };
754 r1md_pins: r1md-pins {
755 groups = "r1md";
756 function = "r1md";
757 };
758 smb3d_pins: smb3d-pins {
759 groups = "smb3d";
760 function = "smb3d";
761 };
762 fanin0_pins: fanin0-pins {
763 groups = "fanin0";
764 function = "fanin0";
765 };
766 fanin1_pins: fanin1-pins {
767 groups = "fanin1";
768 function = "fanin1";
769 };
770 fanin2_pins: fanin2-pins {
771 groups = "fanin2";
772 function = "fanin2";
773 };
774 fanin3_pins: fanin3-pins {
775 groups = "fanin3";
776 function = "fanin3";
777 };
778 fanin4_pins: fanin4-pins {
779 groups = "fanin4";
780 function = "fanin4";
781 };
782 fanin5_pins: fanin5-pins {
783 groups = "fanin5";
784 function = "fanin5";
785 };
786 fanin6_pins: fanin6-pins {
787 groups = "fanin6";
788 function = "fanin6";
789 };
790 fanin7_pins: fanin7-pins {
791 groups = "fanin7";
792 function = "fanin7";
793 };
794 fanin8_pins: fanin8-pins {
795 groups = "fanin8";
796 function = "fanin8";
797 };
798 fanin9_pins: fanin9-pins {
799 groups = "fanin9";
800 function = "fanin9";
801 };
802 fanin10_pins: fanin10-pins {
803 groups = "fanin10";
804 function = "fanin10";
805 };
806 fanin11_pins: fanin11-pins {
807 groups = "fanin11";
808 function = "fanin11";
809 };
810 fanin12_pins: fanin12-pins {
811 groups = "fanin12";
812 function = "fanin12";
813 };
814 fanin13_pins: fanin13-pins {
815 groups = "fanin13";
816 function = "fanin13";
817 };
818 fanin14_pins: fanin14-pins {
819 groups = "fanin14";
820 function = "fanin14";
821 };
822 fanin15_pins: fanin15-pins {
823 groups = "fanin15";
824 function = "fanin15";
825 };
826 pwm0_pins: pwm0-pins {
827 groups = "pwm0";
828 function = "pwm0";
829 };
830 pwm1_pins: pwm1-pins {
831 groups = "pwm1";
832 function = "pwm1";
833 };
834 pwm2_pins: pwm2-pins {
835 groups = "pwm2";
836 function = "pwm2";
837 };
838 pwm3_pins: pwm3-pins {
839 groups = "pwm3";
840 function = "pwm3";
841 };
842 r2_pins: r2-pins {
843 groups = "r2";
844 function = "r2";
845 };
846 r2err_pins: r2err-pins {
847 groups = "r2err";
848 function = "r2err";
849 };
850 r2md_pins: r2md-pins {
851 groups = "r2md";
852 function = "r2md";
853 };
854 ga20kbc_pins: ga20kbc-pins {
855 groups = "ga20kbc";
856 function = "ga20kbc";
857 };
858 smb5d_pins: smb5d-pins {
859 groups = "smb5d";
860 function = "smb5d";
861 };
862 lpc_pins: lpc-pins {
863 groups = "lpc";
864 function = "lpc";
865 };
866 espi_pins: espi-pins {
867 groups = "espi";
868 function = "espi";
869 };
870 rg1_pins: rg1-pins {
871 groups = "rg1";
872 function = "rg1";
873 };
874 rg1mdio_pins: rg1mdio-pins {
875 groups = "rg1mdio";
876 function = "rg1mdio";
877 };
878 rg2_pins: rg2-pins {
879 groups = "rg2";
880 function = "rg2";
881 };
882 ddr_pins: ddr-pins {
883 groups = "ddr";
884 function = "ddr";
885 };
886 smb0_pins: smb0-pins {
887 groups = "smb0";
888 function = "smb0";
889 };
890 smb1_pins: smb1-pins {
891 groups = "smb1";
892 function = "smb1";
893 };
894 smb2_pins: smb2-pins {
895 groups = "smb2";
896 function = "smb2";
897 };
898 smb2c_pins: smb2c-pins {
899 groups = "smb2c";
900 function = "smb2c";
901 };
902 smb2b_pins: smb2b-pins {
903 groups = "smb2b";
904 function = "smb2b";
905 };
906 smb1c_pins: smb1c-pins {
907 groups = "smb1c";
908 function = "smb1c";
909 };
910 smb1b_pins: smb1b-pins {
911 groups = "smb1b";
912 function = "smb1b";
913 };
914 smb8_pins: smb8-pins {
915 groups = "smb8";
916 function = "smb8";
917 };
918 smb9_pins: smb9-pins {
919 groups = "smb9";
920 function = "smb9";
921 };
922 smb10_pins: smb10-pins {
923 groups = "smb10";
924 function = "smb10";
925 };
926 smb11_pins: smb11-pins {
927 groups = "smb11";
928 function = "smb11";
929 };
930 sd1_pins: sd1-pins {
931 groups = "sd1";
932 function = "sd1";
933 };
934 sd1pwr_pins: sd1pwr-pins {
935 groups = "sd1pwr";
936 function = "sd1pwr";
937 };
938 pwm4_pins: pwm4-pins {
939 groups = "pwm4";
940 function = "pwm4";
941 };
942 pwm5_pins: pwm5-pins {
943 groups = "pwm5";
944 function = "pwm5";
945 };
946 pwm6_pins: pwm6-pins {
947 groups = "pwm6";
948 function = "pwm6";
949 };
950 pwm7_pins: pwm7-pins {
951 groups = "pwm7";
952 function = "pwm7";
953 };
954 mmc8_pins: mmc8-pins {
955 groups = "mmc8";
956 function = "mmc8";
957 };
958 mmc_pins: mmc-pins {
959 groups = "mmc";
960 function = "mmc";
961 };
962 mmcwp_pins: mmcwp-pins {
963 groups = "mmcwp";
964 function = "mmcwp";
965 };
966 mmccd_pins: mmccd-pins {
967 groups = "mmccd";
968 function = "mmccd";
969 };
970 mmcrst_pins: mmcrst-pins {
971 groups = "mmcrst";
972 function = "mmcrst";
973 };
974 clkout_pins: clkout-pins {
975 groups = "clkout";
976 function = "clkout";
977 };
978 serirq_pins: serirq-pins {
979 groups = "serirq";
980 function = "serirq";
981 };
982 lpcclk_pins: lpcclk-pins {
983 groups = "lpcclk";
984 function = "lpcclk";
985 };
986 scipme_pins: scipme-pins {
987 groups = "scipme";
988 function = "scipme";
989 };
990 sci_pins: sci-pins {
991 groups = "sci";
992 function = "sci";
993 };
994 smb6_pins: smb6-pins {
995 groups = "smb6";
996 function = "smb6";
997 };
998 smb7_pins: smb7-pins {
999 groups = "smb7";
1000 function = "smb7";
1001 };
1002 pspi1_pins: pspi1-pins {
1003 groups = "pspi1";
1004 function = "pspi1";
1005 };
1006 faninx_pins: faninx-pins {
1007 groups = "faninx";
1008 function = "faninx";
1009 };
1010 r1_pins: r1-pins {
1011 groups = "r1";
1012 function = "r1";
1013 };
1014 spi3_pins: spi3-pins {
1015 groups = "spi3";
1016 function = "spi3";
1017 };
1018 spi3cs1_pins: spi3cs1-pins {
1019 groups = "spi3cs1";
1020 function = "spi3cs1";
1021 };
1022 spi3quad_pins: spi3quad-pins {
1023 groups = "spi3quad";
1024 function = "spi3quad";
1025 };
1026 spi3cs2_pins: spi3cs2-pins {
1027 groups = "spi3cs2";
1028 function = "spi3cs2";
1029 };
1030 spi3cs3_pins: spi3cs3-pins {
1031 groups = "spi3cs3";
1032 function = "spi3cs3";
1033 };
1034 nprd_smi_pins: nprd-smi-pins {
1035 groups = "nprd_smi";
1036 function = "nprd_smi";
1037 };
1038 smb0b_pins: smb0b-pins {
1039 groups = "smb0b";
1040 function = "smb0b";
1041 };
1042 smb0c_pins: smb0c-pins {
1043 groups = "smb0c";
1044 function = "smb0c";
1045 };
1046 smb0den_pins: smb0den-pins {
1047 groups = "smb0den";
1048 function = "smb0den";
1049 };
1050 smb0d_pins: smb0d-pins {
1051 groups = "smb0d";
1052 function = "smb0d";
1053 };
1054 ddc_pins: ddc-pins {
1055 groups = "ddc";
1056 function = "ddc";
1057 };
1058 rg2mdio_pins: rg2mdio-pins {
1059 groups = "rg2mdio";
1060 function = "rg2mdio";
1061 };
1062 wdog1_pins: wdog1-pins {
1063 groups = "wdog1";
1064 function = "wdog1";
1065 };
1066 wdog2_pins: wdog2-pins {
1067 groups = "wdog2";
1068 function = "wdog2";
1069 };
1070 smb12_pins: smb12-pins {
1071 groups = "smb12";
1072 function = "smb12";
1073 };
1074 smb13_pins: smb13-pins {
1075 groups = "smb13";
1076 function = "smb13";
1077 };
1078 spix_pins: spix-pins {
1079 groups = "spix";
1080 function = "spix";
1081 };
1082 spixcs1_pins: spixcs1-pins {
1083 groups = "spixcs1";
1084 function = "spixcs1";
1085 };
1086 clkreq_pins: clkreq-pins {
1087 groups = "clkreq";
1088 function = "clkreq";
1089 };
1090 hgpio0_pins: hgpio0-pins {
1091 groups = "hgpio0";
1092 function = "hgpio0";
1093 };
1094 hgpio1_pins: hgpio1-pins {
1095 groups = "hgpio1";
1096 function = "hgpio1";
1097 };
1098 hgpio2_pins: hgpio2-pins {
1099 groups = "hgpio2";
1100 function = "hgpio2";
1101 };
1102 hgpio3_pins: hgpio3-pins {
1103 groups = "hgpio3";
1104 function = "hgpio3";
1105 };
1106 hgpio4_pins: hgpio4-pins {
1107 groups = "hgpio4";
1108 function = "hgpio4";
1109 };
1110 hgpio5_pins: hgpio5-pins {
1111 groups = "hgpio5";
1112 function = "hgpio5";
1113 };
1114 hgpio6_pins: hgpio6-pins {
1115 groups = "hgpio6";
1116 function = "hgpio6";
1117 };
1118 hgpio7_pins: hgpio7-pins {
1119 groups = "hgpio7";
1120 function = "hgpio7";
1121 };
1122 };
1123};