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git01.mediatek.com / filogic / uboot / d48f49b207b2225d3c90c0a6735ae4239f46af80 / . / arch / arm / dts / fsl-imx8qxp-mek-u-boot.dtsi
blob: ae037c7550df5b7256e345fcc7c1a4ee98244249 [file] [log] [blame]
Peng Fan24063f92018-12-21 06:21:26 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
Gaurav Jainb91e58b2022-03-24 11:50:32 +0530[diff] [blame]3 * Copyright 2018, 2021 NXP
Peng Fan24063f92018-12-21 06:21:26 +0000[diff] [blame]4 */
5
Peng Fana31a5232019-03-07 12:43:37 +0000[diff] [blame]6&{/imx8qx-pm} {
7
8 u-boot,dm-spl;
9};
10
Peng Fan24063f92018-12-21 06:21:26 +0000[diff] [blame]11&mu {
12 u-boot,dm-spl;
13};
14
15&clk {
16 u-boot,dm-spl;
17};
18
19&iomuxc {
20 u-boot,dm-spl;
21};
22
23&pd_lsio {
24 u-boot,dm-spl;
25};
26
27&pd_lsio_gpio0 {
28 u-boot,dm-spl;
29};
30
31&pd_lsio_gpio1 {
32 u-boot,dm-spl;
33};
34
35&pd_lsio_gpio2 {
36 u-boot,dm-spl;
37};
38
39&pd_lsio_gpio3 {
40 u-boot,dm-spl;
41};
42
43&pd_lsio_gpio4 {
44 u-boot,dm-spl;
45};
46
47&pd_lsio_gpio5 {
48 u-boot,dm-spl;
49};
50
51&pd_lsio_gpio6 {
52 u-boot,dm-spl;
53};
54
55&pd_lsio_gpio7 {
56 u-boot,dm-spl;
57};
58
59&pd_conn {
60 u-boot,dm-spl;
61};
62
63&pd_conn_sdch0 {
64 u-boot,dm-spl;
65};
66
67&pd_conn_sdch1 {
68 u-boot,dm-spl;
69};
70
71&pd_conn_sdch2 {
72 u-boot,dm-spl;
73};
74
Peng Fan8064b7e2019-09-02 10:20:12 +0000[diff] [blame]75&pd_dma {
76 u-boot,dm-spl;
77};
78
79&pd_dma_lpuart0 {
80 u-boot,dm-spl;
81};
82
Gaurav Jainb91e58b2022-03-24 11:50:32 +0530[diff] [blame]83&pd_caam {
84 u-boot,dm-spl;
85};
86
87&pd_caam_jr1 {
88 u-boot,dm-spl;
89};
90
91&pd_caam_jr2 {
92 u-boot,dm-spl;
93};
94
95&pd_caam_jr3 {
96 u-boot,dm-spl;
97};
98
Peng Fan24063f92018-12-21 06:21:26 +0000[diff] [blame]99&gpio0 {
100 u-boot,dm-spl;
101};
102
103&gpio1 {
104 u-boot,dm-spl;
105};
106
107&gpio2 {
108 u-boot,dm-spl;
109};
110
111&gpio3 {
112 u-boot,dm-spl;
113};
114
115&gpio4 {
116 u-boot,dm-spl;
117};
118
119&gpio5 {
120 u-boot,dm-spl;
121};
122
123&gpio6 {
124 u-boot,dm-spl;
125};
126
127&gpio7 {
128 u-boot,dm-spl;
129};
130
131&lpuart0 {
132 u-boot,dm-spl;
133};
134
135&usdhc1 {
136 u-boot,dm-spl;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]137 mmc-hs400-1_8v;
Peng Fan24063f92018-12-21 06:21:26 +0000[diff] [blame]138};
139
140&usdhc2 {
141 u-boot,dm-spl;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]142 sd-uhs-sdr104;
143 sd-uhs-ddr50;
Peng Fan24063f92018-12-21 06:21:26 +0000[diff] [blame]144};
Gaurav Jainb91e58b2022-03-24 11:50:32 +0530[diff] [blame]145
146&crypto {
147 u-boot,dm-spl;
148};
149
150&sec_jr1 {
151 u-boot,dm-spl;
152};
153
154&sec_jr2 {
155 u-boot,dm-spl;
156};
157
158&sec_jr3 {
159 u-boot,dm-spl;
160};