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Siva Durga Prasad Paladugu650fb402015-06-10 15:50:57 +05301/*
Michal Simekc1b82162015-08-20 15:21:48 +02002 * Configuration for Xilinx ZynqMP emulation platforms
Siva Durga Prasad Paladugu650fb402015-06-10 15:50:57 +05303 *
4 * (C) Copyright 2014 - 2015 Xilinx, Inc.
5 * Michal Simek <michal.simek@xilinx.com>
6 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
7 *
8 * Based on Configuration for Versatile Express
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#ifndef __CONFIG_ZYNQMP_EP_H
14#define __CONFIG_ZYNQMP_EP_H
15
Siva Durga Prasad Paladugu650fb402015-06-10 15:50:57 +053016#define CONFIG_ZYNQ_SDHCI0
Michal Simek8bc78172015-09-29 01:27:13 +020017#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
Siva Durga Prasad Paladuguac001512016-01-05 12:21:05 +053018#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9)
Siva Durga Prasad Paladugu650fb402015-06-10 15:50:57 +053019#define CONFIG_ZYNQ_I2C0
20#define CONFIG_SYS_I2C_ZYNQ
21#define CONFIG_ZYNQ_EEPROM
Michal Simekb216cc12015-07-23 13:27:40 +020022#define CONFIG_AHCI
Siva Durga Prasad Paladuguee8dc842015-11-16 16:49:23 +053023#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
24 ZYNQMP_USB1_XHCI_BASEADDR}
Siva Durga Prasad Paladugu650fb402015-06-10 15:50:57 +053025
Michal Simek503a76f2015-10-05 11:02:33 +020026/* Physical Memory Map */
27#define CONFIG_NR_DRAM_BANKS 1
28#define CONFIG_SYS_SDRAM_BASE 0
29#define CONFIG_SYS_SDRAM_SIZE 0x40000000
30
Michal Simekd48a1702015-11-05 08:32:14 +010031#define COUNTER_FREQUENCY 4000000
32
Siva Durga Prasad Paladugu650fb402015-06-10 15:50:57 +053033#include <configs/xilinx_zynqmp.h>
34
35#endif /* __CONFIG_ZYNQMP_EP_H */