| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Bo Shen | 2b22cb8 | 2014-12-15 13:24:28 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Bus Matrix header file for the SAMA5 family |
| 4 | * |
| 5 | * Copyright (C) 2014 Atmel |
| 6 | * Bo Shen <voice.shen@atmel.com> |
| Bo Shen | 2b22cb8 | 2014-12-15 13:24:28 +0800 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __SAMA5_MATRIX_H |
| 10 | #define __SAMA5_MATRIX_H |
| 11 | |
| 12 | struct atmel_matrix { |
| 13 | u32 mcfg[16]; /* 0x00 ~ 0x3c: Master Configuration Register */ |
| 14 | u32 scfg[16]; /* 0x40 ~ 0x7c: Slave Configuration Register */ |
| 15 | u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */ |
| 16 | u32 res1[20]; /* 0x100 ~ 0x14c */ |
| 17 | u32 meier; /* 0x150: Master Error Interrupt Enable Register */ |
| 18 | u32 meidr; /* 0x154: Master Error Interrupt Disable Register */ |
| 19 | u32 meimr; /* 0x158: Master Error Interrupt Mask Register */ |
| 20 | u32 mesr; /* 0x15c: Master Error Status Register */ |
| 21 | u32 mear[16]; /* 0x160 ~ 0x19c: Master Error Address Register */ |
| 22 | u32 res2[17]; /* 0x1A0 ~ 0x1E0 */ |
| 23 | u32 wpmr; /* 0x1E4: Write Protection Mode Register */ |
| 24 | u32 wpsr; /* 0x1E8: Write Protection Status Register */ |
| 25 | u32 res3[5]; /* 0x1EC ~ 0x1FC */ |
| 26 | u32 ssr[16]; /* 0x200 ~ 0x23c: Security Slave Register */ |
| 27 | u32 sassr[16]; /* 0x240 ~ 0x27c: Security Areas Split Slave Register */ |
| 28 | u32 srtsr[16]; /* 0x280 ~ 0x2bc: Security Region Top Slave */ |
| 29 | u32 spselr[3]; /* 0x2c0 ~ 0x2c8: Security Peripheral Select Register */ |
| 30 | }; |
| 31 | |
| 32 | /* Bit field in WPMR */ |
| 33 | #define ATMEL_MATRIX_WPMR_WPKEY 0x4D415400 |
| 34 | #define ATMEL_MATRIX_WPMR_WPEN 0x00000001 |
| 35 | |
| 36 | #endif |