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Michal Simek04b7e622015-01-15 10:01:51 +01001/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <netdev.h>
Michal Simekb216cc12015-07-23 13:27:40 +020010#include <ahci.h>
11#include <scsi.h>
Michal Simekc23d3f82015-11-05 08:34:35 +010012#include <asm/arch/clk.h>
Michal Simek04b7e622015-01-15 10:01:51 +010013#include <asm/arch/hardware.h>
14#include <asm/arch/sys_proto.h>
15#include <asm/io.h>
Siva Durga Prasad Paladuguba1f68e2015-08-04 13:03:26 +053016#include <usb.h>
17#include <dwc3-uboot.h>
Michal Simek04b7e622015-01-15 10:01:51 +010018
19DECLARE_GLOBAL_DATA_PTR;
20
21int board_init(void)
22{
Michal Simekfb7242d2015-06-22 14:31:06 +020023 printf("EL Level:\tEL%d\n", current_el());
24
Michal Simek04b7e622015-01-15 10:01:51 +010025 return 0;
26}
27
28int board_early_init_r(void)
29{
30 u32 val;
31
Michal Simekc23d3f82015-11-05 08:34:35 +010032 if (current_el() == 3) {
33 val = readl(&crlapb_base->timestamp_ref_ctrl);
34 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
35 writel(val, &crlapb_base->timestamp_ref_ctrl);
Michal Simek04b7e622015-01-15 10:01:51 +010036
Michal Simekc23d3f82015-11-05 08:34:35 +010037 /* Program freq register in System counter */
38 writel(zynqmp_get_system_timer_freq(),
39 &iou_scntr_secure->base_frequency_id_register);
40 /* And enable system counter */
41 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
42 &iou_scntr_secure->counter_control_register);
43 }
Michal Simek04b7e622015-01-15 10:01:51 +010044 /* Program freq register in System counter and enable system counter */
45 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
46 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
47 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
48 &iou_scntr->counter_control_register);
49
50 return 0;
51}
52
53int dram_init(void)
54{
55 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
56
57 return 0;
58}
59
Michal Simek04b7e622015-01-15 10:01:51 +010060void reset_cpu(ulong addr)
61{
62}
63
Michal Simekb216cc12015-07-23 13:27:40 +020064#ifdef CONFIG_SCSI_AHCI_PLAT
65void scsi_init(void)
66{
67 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
68 scsi_scan(1);
69}
70#endif
71
Michal Simek04b7e622015-01-15 10:01:51 +010072int board_late_init(void)
73{
74 u32 reg = 0;
75 u8 bootmode;
76
77 reg = readl(&crlapb_base->boot_mode);
78 bootmode = reg & BOOT_MODES_MASK;
79
Michal Simekc5d95232015-09-20 17:20:42 +020080 puts("Bootmode: ");
Michal Simek04b7e622015-01-15 10:01:51 +010081 switch (bootmode) {
Siva Durga Prasad Paladugu30f0fc72015-03-13 11:10:26 +053082 case JTAG_MODE:
Michal Simekc5d95232015-09-20 17:20:42 +020083 puts("JTAG_MODE\n");
84 setenv("modeboot", "jtagboot");
Siva Durga Prasad Paladugu30f0fc72015-03-13 11:10:26 +053085 break;
86 case QSPI_MODE_24BIT:
87 case QSPI_MODE_32BIT:
88 setenv("modeboot", "qspiboot");
Michal Simekc5d95232015-09-20 17:20:42 +020089 puts("QSPI_MODE\n");
Siva Durga Prasad Paladugu30f0fc72015-03-13 11:10:26 +053090 break;
Michal Simek02d66cd2015-04-15 15:02:28 +020091 case EMMC_MODE:
Michal Simekdf7ff0a2015-10-05 15:59:38 +020092 puts("EMMC_MODE\n");
93 setenv("modeboot", "sdboot");
94 break;
95 case SD_MODE:
Michal Simekc5d95232015-09-20 17:20:42 +020096 puts("SD_MODE\n");
Michal Simek04b7e622015-01-15 10:01:51 +010097 setenv("modeboot", "sdboot");
98 break;
Michal Simek108e1842015-10-05 10:51:12 +020099 case SD_MODE1:
Michal Simekc5d95232015-09-20 17:20:42 +0200100 puts("SD_MODE1\n");
Michal Simek6d902452015-11-06 10:22:37 +0100101#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
102 setenv("sdbootdev", "1");
103#endif
104 setenv("modeboot", "sdboot");
Michal Simek108e1842015-10-05 10:51:12 +0200105 break;
106 case NAND_MODE:
Michal Simekc5d95232015-09-20 17:20:42 +0200107 puts("NAND_MODE\n");
Michal Simek108e1842015-10-05 10:51:12 +0200108 setenv("modeboot", "nandboot");
109 break;
Michal Simek04b7e622015-01-15 10:01:51 +0100110 default:
111 printf("Invalid Boot Mode:0x%x\n", bootmode);
112 break;
113 }
114
115 return 0;
116}
Siva Durga Prasad Paladugu650e0a32015-08-04 13:01:05 +0530117
118int checkboard(void)
119{
Michal Simek47ce9362016-01-25 11:04:21 +0100120 puts("Board: Xilinx ZynqMP\n");
Siva Durga Prasad Paladugu650e0a32015-08-04 13:01:05 +0530121 return 0;
122}
Siva Durga Prasad Paladuguba1f68e2015-08-04 13:03:26 +0530123
124#ifdef CONFIG_USB_DWC3
125static struct dwc3_device dwc3_device_data = {
126 .maximum_speed = USB_SPEED_HIGH,
127 .base = ZYNQMP_USB0_XHCI_BASEADDR,
128 .dr_mode = USB_DR_MODE_PERIPHERAL,
129 .index = 0,
130};
131
132int usb_gadget_handle_interrupts(void)
133{
134 dwc3_uboot_handle_interrupt(0);
135 return 0;
136}
137
138int board_usb_init(int index, enum usb_init_type init)
139{
140 return dwc3_uboot_init(&dwc3_device_data);
141}
142
143int board_usb_cleanup(int index, enum usb_init_type init)
144{
145 dwc3_uboot_exit(index);
146 return 0;
147}
148#endif