Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 1 | /* |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 2 | * Keystone : Board initialization |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 3 | * |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 4 | * (C) Copyright 2014 |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 5 | * Texas Instruments Incorporated, <www.ti.com> |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 10 | #include "board.h" |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 11 | #include <common.h> |
Hao Zhang | 9594820 | 2014-10-22 16:32:31 +0300 | [diff] [blame] | 12 | #include <spl.h> |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 13 | #include <exports.h> |
| 14 | #include <fdt_support.h> |
Khoronzhuk, Ivan | 50df5cc | 2014-07-09 19:48:40 +0300 | [diff] [blame] | 15 | #include <asm/arch/ddr3.h> |
Khoronzhuk, Ivan | 238de85 | 2014-09-29 22:17:24 +0300 | [diff] [blame] | 16 | #include <asm/arch/psc_defs.h> |
Lokesh Vutla | da18b18 | 2015-10-08 11:31:47 +0530 | [diff] [blame] | 17 | #include <asm/arch/clock.h> |
Khoronzhuk, Ivan | 8062b05 | 2014-06-07 05:10:49 +0300 | [diff] [blame] | 18 | #include <asm/ti-common/ti-aemif.h> |
Khoronzhuk, Ivan | f2c13ba | 2014-09-29 22:17:22 +0300 | [diff] [blame] | 19 | #include <asm/ti-common/keystone_net.h> |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 20 | |
| 21 | DECLARE_GLOBAL_DATA_PTR; |
| 22 | |
Khoronzhuk, Ivan | 8062b05 | 2014-06-07 05:10:49 +0300 | [diff] [blame] | 23 | static struct aemif_config aemif_configs[] = { |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 24 | { /* CS0 */ |
Khoronzhuk, Ivan | 8062b05 | 2014-06-07 05:10:49 +0300 | [diff] [blame] | 25 | .mode = AEMIF_MODE_NAND, |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 26 | .wr_setup = 0xf, |
| 27 | .wr_strobe = 0x3f, |
| 28 | .wr_hold = 7, |
| 29 | .rd_setup = 0xf, |
| 30 | .rd_strobe = 0x3f, |
| 31 | .rd_hold = 7, |
| 32 | .turn_around = 3, |
Khoronzhuk, Ivan | 8062b05 | 2014-06-07 05:10:49 +0300 | [diff] [blame] | 33 | .width = AEMIF_WIDTH_8, |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 34 | }, |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 35 | }; |
| 36 | |
| 37 | int dram_init(void) |
| 38 | { |
Vitaly Andrianov | a9554d6 | 2015-02-11 14:07:58 -0500 | [diff] [blame] | 39 | u32 ddr3_size; |
| 40 | |
| 41 | ddr3_size = ddr3_init(); |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 42 | |
| 43 | gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, |
| 44 | CONFIG_MAX_RAM_BANK_SIZE); |
Khoronzhuk, Ivan | 8062b05 | 2014-06-07 05:10:49 +0300 | [diff] [blame] | 45 | aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); |
Vitaly Andrianov | bbf8ac2 | 2015-09-19 16:26:43 +0530 | [diff] [blame] | 46 | if (ddr3_size) |
| 47 | ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 48 | return 0; |
| 49 | } |
| 50 | |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 51 | int board_init(void) |
| 52 | { |
Nishanth Menon | 842649d | 2015-07-22 18:05:43 -0500 | [diff] [blame] | 53 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 54 | |
| 55 | return 0; |
| 56 | } |
Karicheri, Muralidharan | 657f6b5 | 2014-04-01 15:01:13 -0400 | [diff] [blame] | 57 | |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 58 | #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET |
Karicheri, Muralidharan | 657f6b5 | 2014-04-01 15:01:13 -0400 | [diff] [blame] | 59 | int get_eth_env_param(char *env_name) |
| 60 | { |
| 61 | char *env; |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 62 | int res = -1; |
Karicheri, Muralidharan | 657f6b5 | 2014-04-01 15:01:13 -0400 | [diff] [blame] | 63 | |
| 64 | env = getenv(env_name); |
| 65 | if (env) |
| 66 | res = simple_strtol(env, NULL, 0); |
| 67 | |
| 68 | return res; |
| 69 | } |
| 70 | |
| 71 | int board_eth_init(bd_t *bis) |
| 72 | { |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 73 | int j; |
| 74 | int res; |
| 75 | int port_num; |
| 76 | char link_type_name[32]; |
Karicheri, Muralidharan | 657f6b5 | 2014-04-01 15:01:13 -0400 | [diff] [blame] | 77 | |
Khoronzhuk, Ivan | 238de85 | 2014-09-29 22:17:24 +0300 | [diff] [blame] | 78 | /* By default, select PA PLL clock as PA clock source */ |
| 79 | if (psc_enable_module(KS2_LPSC_PA)) |
| 80 | return -1; |
| 81 | if (psc_enable_module(KS2_LPSC_CPGMAC)) |
| 82 | return -1; |
| 83 | if (psc_enable_module(KS2_LPSC_CRYPTO)) |
| 84 | return -1; |
| 85 | |
Lokesh Vutla | da18b18 | 2015-10-08 11:31:47 +0530 | [diff] [blame] | 86 | if (cpu_is_k2e() || cpu_is_k2l()) |
| 87 | pll_pa_clk_sel(); |
| 88 | |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 89 | port_num = get_num_eth_ports(); |
| 90 | |
| 91 | for (j = 0; j < port_num; j++) { |
Karicheri, Muralidharan | 657f6b5 | 2014-04-01 15:01:13 -0400 | [diff] [blame] | 92 | sprintf(link_type_name, "sgmii%d_link_type", j); |
| 93 | res = get_eth_env_param(link_type_name); |
| 94 | if (res >= 0) |
| 95 | eth_priv_cfg[j].sgmii_link_type = res; |
| 96 | |
| 97 | keystone2_emac_initialize(ð_priv_cfg[j]); |
| 98 | } |
| 99 | |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 100 | return 0; |
| 101 | } |
| 102 | #endif |
| 103 | |
Hao Zhang | 9594820 | 2014-10-22 16:32:31 +0300 | [diff] [blame] | 104 | #ifdef CONFIG_SPL_BUILD |
| 105 | void spl_board_init(void) |
| 106 | { |
| 107 | spl_init_keystone_plls(); |
| 108 | preloader_console_init(); |
| 109 | } |
| 110 | |
| 111 | u32 spl_boot_device(void) |
| 112 | { |
| 113 | #if defined(CONFIG_SPL_SPI_LOAD) |
| 114 | return BOOT_DEVICE_SPI; |
| 115 | #else |
| 116 | puts("Unknown boot device\n"); |
| 117 | hang(); |
| 118 | #endif |
| 119 | } |
| 120 | #endif |
| 121 | |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 122 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 123 | int ft_board_setup(void *blob, bd_t *bd) |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 124 | { |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 125 | int lpae; |
| 126 | char *env; |
| 127 | char *endp; |
| 128 | int nbanks; |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 129 | u64 size[2]; |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 130 | u64 start[2]; |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 131 | int nodeoffset; |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 132 | u32 ddr3a_size; |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 133 | int unitrd_fixup = 0; |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 134 | |
| 135 | env = getenv("mem_lpae"); |
| 136 | lpae = env && simple_strtol(env, NULL, 0); |
Murali Karicheri | 1b84532 | 2014-07-09 23:44:45 +0300 | [diff] [blame] | 137 | env = getenv("uinitrd_fixup"); |
| 138 | unitrd_fixup = env && simple_strtol(env, NULL, 0); |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 139 | |
| 140 | ddr3a_size = 0; |
| 141 | if (lpae) { |
| 142 | env = getenv("ddr3a_size"); |
| 143 | if (env) |
| 144 | ddr3a_size = simple_strtol(env, NULL, 10); |
| 145 | if ((ddr3a_size != 8) && (ddr3a_size != 4)) |
| 146 | ddr3a_size = 0; |
| 147 | } |
| 148 | |
| 149 | nbanks = 1; |
| 150 | start[0] = bd->bi_dram[0].start; |
| 151 | size[0] = bd->bi_dram[0].size; |
| 152 | |
| 153 | /* adjust memory start address for LPAE */ |
| 154 | if (lpae) { |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 155 | start[0] -= CONFIG_SYS_SDRAM_BASE; |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 156 | start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; |
| 157 | } |
| 158 | |
| 159 | if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { |
| 160 | size[1] = ((u64)ddr3a_size - 2) << 30; |
| 161 | start[1] = 0x880000000; |
| 162 | nbanks++; |
| 163 | } |
| 164 | |
| 165 | /* reserve memory at start of bank */ |
Khoronzhuk, Ivan | 46e6517 | 2014-11-04 20:48:47 +0200 | [diff] [blame] | 166 | env = getenv("mem_reserve_head"); |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 167 | if (env) { |
| 168 | start[0] += ustrtoul(env, &endp, 0); |
| 169 | size[0] -= ustrtoul(env, &endp, 0); |
| 170 | } |
| 171 | |
Khoronzhuk, Ivan | 46e6517 | 2014-11-04 20:48:47 +0200 | [diff] [blame] | 172 | env = getenv("mem_reserve"); |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 173 | if (env) |
| 174 | size[0] -= ustrtoul(env, &endp, 0); |
| 175 | |
| 176 | fdt_fixup_memory_banks(blob, start, size, nbanks); |
| 177 | |
| 178 | /* Fix up the initrd */ |
Murali Karicheri | 1b84532 | 2014-07-09 23:44:45 +0300 | [diff] [blame] | 179 | if (lpae && unitrd_fixup) { |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 180 | int err; |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 181 | u32 *prop1, *prop2; |
| 182 | u64 initrd_start, initrd_end; |
Murali Karicheri | 1b84532 | 2014-07-09 23:44:45 +0300 | [diff] [blame] | 183 | |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 184 | nodeoffset = fdt_path_offset(blob, "/chosen"); |
| 185 | if (nodeoffset >= 0) { |
| 186 | prop1 = (u32 *)fdt_getprop(blob, nodeoffset, |
| 187 | "linux,initrd-start", NULL); |
| 188 | prop2 = (u32 *)fdt_getprop(blob, nodeoffset, |
| 189 | "linux,initrd-end", NULL); |
| 190 | if (prop1 && prop2) { |
| 191 | initrd_start = __be32_to_cpu(*prop1); |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 192 | initrd_start -= CONFIG_SYS_SDRAM_BASE; |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 193 | initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; |
| 194 | initrd_start = __cpu_to_be64(initrd_start); |
| 195 | initrd_end = __be32_to_cpu(*prop2); |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 196 | initrd_end -= CONFIG_SYS_SDRAM_BASE; |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 197 | initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; |
| 198 | initrd_end = __cpu_to_be64(initrd_end); |
| 199 | |
| 200 | err = fdt_delprop(blob, nodeoffset, |
| 201 | "linux,initrd-start"); |
| 202 | if (err < 0) |
| 203 | puts("error deleting initrd-start\n"); |
| 204 | |
| 205 | err = fdt_delprop(blob, nodeoffset, |
| 206 | "linux,initrd-end"); |
| 207 | if (err < 0) |
| 208 | puts("error deleting initrd-end\n"); |
| 209 | |
| 210 | err = fdt_setprop(blob, nodeoffset, |
| 211 | "linux,initrd-start", |
| 212 | &initrd_start, |
| 213 | sizeof(initrd_start)); |
| 214 | if (err < 0) |
| 215 | puts("error adding initrd-start\n"); |
| 216 | |
| 217 | err = fdt_setprop(blob, nodeoffset, |
| 218 | "linux,initrd-end", |
| 219 | &initrd_end, |
| 220 | sizeof(initrd_end)); |
| 221 | if (err < 0) |
| 222 | puts("error adding linux,initrd-end\n"); |
| 223 | } |
| 224 | } |
| 225 | } |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 226 | |
| 227 | return 0; |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 228 | } |
| 229 | |
| 230 | void ft_board_setup_ex(void *blob, bd_t *bd) |
| 231 | { |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 232 | int lpae; |
| 233 | u64 size; |
| 234 | char *env; |
| 235 | u64 *reserve_start; |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 236 | |
| 237 | env = getenv("mem_lpae"); |
| 238 | lpae = env && simple_strtol(env, NULL, 0); |
| 239 | |
| 240 | if (lpae) { |
| 241 | /* |
| 242 | * the initrd and other reserved memory areas are |
| 243 | * embedded in in the DTB itslef. fix up these addresses |
| 244 | * to 36 bit format |
| 245 | */ |
| 246 | reserve_start = (u64 *)((char *)blob + |
| 247 | fdt_off_mem_rsvmap(blob)); |
| 248 | while (1) { |
| 249 | *reserve_start = __cpu_to_be64(*reserve_start); |
| 250 | size = __cpu_to_be64(*(reserve_start + 1)); |
| 251 | if (size) { |
Hao Zhang | 8e697a0 | 2014-07-09 23:44:46 +0300 | [diff] [blame] | 252 | *reserve_start -= CONFIG_SYS_SDRAM_BASE; |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 253 | *reserve_start += |
| 254 | CONFIG_SYS_LPAE_SDRAM_BASE; |
| 255 | *reserve_start = |
| 256 | __cpu_to_be64(*reserve_start); |
| 257 | } else { |
| 258 | break; |
| 259 | } |
| 260 | reserve_start += 2; |
| 261 | } |
| 262 | } |
Vitaly Andrianov | 1917301 | 2014-10-22 17:47:58 +0300 | [diff] [blame] | 263 | |
| 264 | ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE); |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 265 | } |
| 266 | #endif |