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Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -04001/*
Hao Zhang8e697a02014-07-09 23:44:46 +03002 * Keystone : Board initialization
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -04003 *
Hao Zhang8e697a02014-07-09 23:44:46 +03004 * (C) Copyright 2014
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -04005 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
Hao Zhang8e697a02014-07-09 23:44:46 +030010#include "board.h"
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040011#include <common.h>
Hao Zhang95948202014-10-22 16:32:31 +030012#include <spl.h>
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040013#include <exports.h>
14#include <fdt_support.h>
Khoronzhuk, Ivan50df5cc2014-07-09 19:48:40 +030015#include <asm/arch/ddr3.h>
Khoronzhuk, Ivan238de852014-09-29 22:17:24 +030016#include <asm/arch/psc_defs.h>
Lokesh Vutlada18b182015-10-08 11:31:47 +053017#include <asm/arch/clock.h>
Khoronzhuk, Ivan8062b052014-06-07 05:10:49 +030018#include <asm/ti-common/ti-aemif.h>
Khoronzhuk, Ivanf2c13ba2014-09-29 22:17:22 +030019#include <asm/ti-common/keystone_net.h>
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040020
21DECLARE_GLOBAL_DATA_PTR;
22
Khoronzhuk, Ivan8062b052014-06-07 05:10:49 +030023static struct aemif_config aemif_configs[] = {
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040024 { /* CS0 */
Khoronzhuk, Ivan8062b052014-06-07 05:10:49 +030025 .mode = AEMIF_MODE_NAND,
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040026 .wr_setup = 0xf,
27 .wr_strobe = 0x3f,
28 .wr_hold = 7,
29 .rd_setup = 0xf,
30 .rd_strobe = 0x3f,
31 .rd_hold = 7,
32 .turn_around = 3,
Khoronzhuk, Ivan8062b052014-06-07 05:10:49 +030033 .width = AEMIF_WIDTH_8,
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040034 },
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040035};
36
37int dram_init(void)
38{
Vitaly Andrianova9554d62015-02-11 14:07:58 -050039 u32 ddr3_size;
40
41 ddr3_size = ddr3_init();
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040042
43 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
44 CONFIG_MAX_RAM_BANK_SIZE);
Khoronzhuk, Ivan8062b052014-06-07 05:10:49 +030045 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
Vitaly Andrianovbbf8ac22015-09-19 16:26:43 +053046 if (ddr3_size)
47 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040048 return 0;
49}
50
Hao Zhang8e697a02014-07-09 23:44:46 +030051int board_init(void)
52{
Nishanth Menon842649d2015-07-22 18:05:43 -050053 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
Hao Zhang8e697a02014-07-09 23:44:46 +030054
55 return 0;
56}
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040057
Hao Zhang8e697a02014-07-09 23:44:46 +030058#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040059int get_eth_env_param(char *env_name)
60{
61 char *env;
Hao Zhang8e697a02014-07-09 23:44:46 +030062 int res = -1;
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040063
64 env = getenv(env_name);
65 if (env)
66 res = simple_strtol(env, NULL, 0);
67
68 return res;
69}
70
71int board_eth_init(bd_t *bis)
72{
Hao Zhang8e697a02014-07-09 23:44:46 +030073 int j;
74 int res;
75 int port_num;
76 char link_type_name[32];
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040077
Khoronzhuk, Ivan238de852014-09-29 22:17:24 +030078 /* By default, select PA PLL clock as PA clock source */
79 if (psc_enable_module(KS2_LPSC_PA))
80 return -1;
81 if (psc_enable_module(KS2_LPSC_CPGMAC))
82 return -1;
83 if (psc_enable_module(KS2_LPSC_CRYPTO))
84 return -1;
85
Lokesh Vutlada18b182015-10-08 11:31:47 +053086 if (cpu_is_k2e() || cpu_is_k2l())
87 pll_pa_clk_sel();
88
Hao Zhang8e697a02014-07-09 23:44:46 +030089 port_num = get_num_eth_ports();
90
91 for (j = 0; j < port_num; j++) {
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040092 sprintf(link_type_name, "sgmii%d_link_type", j);
93 res = get_eth_env_param(link_type_name);
94 if (res >= 0)
95 eth_priv_cfg[j].sgmii_link_type = res;
96
97 keystone2_emac_initialize(&eth_priv_cfg[j]);
98 }
99
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400100 return 0;
101}
102#endif
103
Hao Zhang95948202014-10-22 16:32:31 +0300104#ifdef CONFIG_SPL_BUILD
105void spl_board_init(void)
106{
107 spl_init_keystone_plls();
108 preloader_console_init();
109}
110
111u32 spl_boot_device(void)
112{
113#if defined(CONFIG_SPL_SPI_LOAD)
114 return BOOT_DEVICE_SPI;
115#else
116 puts("Unknown boot device\n");
117 hang();
118#endif
119}
120#endif
121
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400122#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Simon Glass2aec3cc2014-10-23 18:58:47 -0600123int ft_board_setup(void *blob, bd_t *bd)
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400124{
Hao Zhang8e697a02014-07-09 23:44:46 +0300125 int lpae;
126 char *env;
127 char *endp;
128 int nbanks;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400129 u64 size[2];
Hao Zhang8e697a02014-07-09 23:44:46 +0300130 u64 start[2];
Hao Zhang8e697a02014-07-09 23:44:46 +0300131 int nodeoffset;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400132 u32 ddr3a_size;
Hao Zhang8e697a02014-07-09 23:44:46 +0300133 int unitrd_fixup = 0;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400134
135 env = getenv("mem_lpae");
136 lpae = env && simple_strtol(env, NULL, 0);
Murali Karicheri1b845322014-07-09 23:44:45 +0300137 env = getenv("uinitrd_fixup");
138 unitrd_fixup = env && simple_strtol(env, NULL, 0);
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400139
140 ddr3a_size = 0;
141 if (lpae) {
142 env = getenv("ddr3a_size");
143 if (env)
144 ddr3a_size = simple_strtol(env, NULL, 10);
145 if ((ddr3a_size != 8) && (ddr3a_size != 4))
146 ddr3a_size = 0;
147 }
148
149 nbanks = 1;
150 start[0] = bd->bi_dram[0].start;
151 size[0] = bd->bi_dram[0].size;
152
153 /* adjust memory start address for LPAE */
154 if (lpae) {
Hao Zhang8e697a02014-07-09 23:44:46 +0300155 start[0] -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400156 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
157 }
158
159 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
160 size[1] = ((u64)ddr3a_size - 2) << 30;
161 start[1] = 0x880000000;
162 nbanks++;
163 }
164
165 /* reserve memory at start of bank */
Khoronzhuk, Ivan46e65172014-11-04 20:48:47 +0200166 env = getenv("mem_reserve_head");
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400167 if (env) {
168 start[0] += ustrtoul(env, &endp, 0);
169 size[0] -= ustrtoul(env, &endp, 0);
170 }
171
Khoronzhuk, Ivan46e65172014-11-04 20:48:47 +0200172 env = getenv("mem_reserve");
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400173 if (env)
174 size[0] -= ustrtoul(env, &endp, 0);
175
176 fdt_fixup_memory_banks(blob, start, size, nbanks);
177
178 /* Fix up the initrd */
Murali Karicheri1b845322014-07-09 23:44:45 +0300179 if (lpae && unitrd_fixup) {
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400180 int err;
Hao Zhang8e697a02014-07-09 23:44:46 +0300181 u32 *prop1, *prop2;
182 u64 initrd_start, initrd_end;
Murali Karicheri1b845322014-07-09 23:44:45 +0300183
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400184 nodeoffset = fdt_path_offset(blob, "/chosen");
185 if (nodeoffset >= 0) {
186 prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
187 "linux,initrd-start", NULL);
188 prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
189 "linux,initrd-end", NULL);
190 if (prop1 && prop2) {
191 initrd_start = __be32_to_cpu(*prop1);
Hao Zhang8e697a02014-07-09 23:44:46 +0300192 initrd_start -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400193 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
194 initrd_start = __cpu_to_be64(initrd_start);
195 initrd_end = __be32_to_cpu(*prop2);
Hao Zhang8e697a02014-07-09 23:44:46 +0300196 initrd_end -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400197 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
198 initrd_end = __cpu_to_be64(initrd_end);
199
200 err = fdt_delprop(blob, nodeoffset,
201 "linux,initrd-start");
202 if (err < 0)
203 puts("error deleting initrd-start\n");
204
205 err = fdt_delprop(blob, nodeoffset,
206 "linux,initrd-end");
207 if (err < 0)
208 puts("error deleting initrd-end\n");
209
210 err = fdt_setprop(blob, nodeoffset,
211 "linux,initrd-start",
212 &initrd_start,
213 sizeof(initrd_start));
214 if (err < 0)
215 puts("error adding initrd-start\n");
216
217 err = fdt_setprop(blob, nodeoffset,
218 "linux,initrd-end",
219 &initrd_end,
220 sizeof(initrd_end));
221 if (err < 0)
222 puts("error adding linux,initrd-end\n");
223 }
224 }
225 }
Simon Glass2aec3cc2014-10-23 18:58:47 -0600226
227 return 0;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400228}
229
230void ft_board_setup_ex(void *blob, bd_t *bd)
231{
Hao Zhang8e697a02014-07-09 23:44:46 +0300232 int lpae;
233 u64 size;
234 char *env;
235 u64 *reserve_start;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400236
237 env = getenv("mem_lpae");
238 lpae = env && simple_strtol(env, NULL, 0);
239
240 if (lpae) {
241 /*
242 * the initrd and other reserved memory areas are
243 * embedded in in the DTB itslef. fix up these addresses
244 * to 36 bit format
245 */
246 reserve_start = (u64 *)((char *)blob +
247 fdt_off_mem_rsvmap(blob));
248 while (1) {
249 *reserve_start = __cpu_to_be64(*reserve_start);
250 size = __cpu_to_be64(*(reserve_start + 1));
251 if (size) {
Hao Zhang8e697a02014-07-09 23:44:46 +0300252 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400253 *reserve_start +=
254 CONFIG_SYS_LPAE_SDRAM_BASE;
255 *reserve_start =
256 __cpu_to_be64(*reserve_start);
257 } else {
258 break;
259 }
260 reserve_start += 2;
261 }
262 }
Vitaly Andrianov19173012014-10-22 17:47:58 +0300263
264 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400265}
266#endif